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Power Regulation in High Performance Multicore Processors
[article]
2017
arXiv
pre-print
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In this it trades modeling precision for fast computations in the loop making it suitable for on-line implementation in commodity data-center processors. ...
This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain. ...
In the context of computer processors, this technique was applied to regulate instructions' throughput. ...
arXiv:1709.04859v1
fatcat:3wcfv5okcfbd7pvojsmvvk7xo4
Web search using mobile cores
2010
Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10
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While these cores can deliver performance-per-Watt efficiency for data center workloads, small cores impact application quality-of-service robustness, and flexibility, as these workloads increasingly invoke ...
Recent advances in mobile computing have led to modern small cores capable of delivering even better power efficiency. ...
Data is normalized with respect to activity on each processor at its sustainable throughput. ...
doi:10.1145/1815961.1816002
dblp:conf/isca/ReddiLCV10
fatcat:w6345inwcjfizdvx7ur2jgyfgu
Web search using mobile cores
2010
SIGARCH Computer Architecture News
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While these cores can deliver performance-per-Watt efficiency for data center workloads, small cores impact application quality-of-service robustness, and flexibility, as these workloads increasingly invoke ...
Recent advances in mobile computing have led to modern small cores capable of delivering even better power efficiency. ...
Data is normalized with respect to activity on each processor at its sustainable throughput. ...
doi:10.1145/1816038.1816002
fatcat:lfvshqx4lfdd3frkusatjegldu
Mobile processors for energy-efficient web search
2011
ACM Transactions on Computer Systems
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After optimizing the Atom server platform, a large share of power and cost go toward processor capability. With optimized Atoms, more servers can fit in a given data center power budget. ...
For a data center with 15MW critical load, Atom-based servers increase capability by 3.2× for Bing. ...
interactions with emerging data center applications. ...
doi:10.1145/2003690.2003693
fatcat:6nqw6324tve6phpauc5fyo6ctq
An Empirical-cum-Statistical Approach to Power-Performance Characterization of Concurrent GPU Kernels
[article]
2020
arXiv
pre-print
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Growing deployment of power and energy efficient throughput accelerators (GPU) in data centers demands enhancement of power-performance co-optimization capabilities of GPUs. ...
With hardwired kernel concurrency enablement in accelerators, inter- and intra-workload simultaneous kernels computation predicts increased throughput at lower energy budget. ...
7] ), IBM Cell processors [8] are increasingly adopted to solve high performance computing problems [9] [10] [11] [12] [13] [14] in data centers [15] [16] [17] [18] [19] and supercomputers (Tianhe ...
arXiv:2011.02368v2
fatcat:xgce6gvcjjcilfwem452yd3hsi
Guest editorial: special issue on performance analysis and optimization of discrete event systems
2018
Discrete event dynamic systems
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After consultation with colleagues following the last International Workshop on DES (WODES 2016, May 2016 in Xian, China), we invited seventeen groups of authors to submit papers for these two special ...
Markov chains and Markov decision processes, simulation-based optimization and new approaches for the performance regulation of DES. ...
Finally, the sixth paper, "Instruction-throughput regulation in computer processors with data-center applications" by Chen, Wardi, and Yalamanchili, considers a recent approach for regulating output performance ...
doi:10.1007/s10626-018-0266-0
fatcat:3jpqnxgunvfrnplw36hzgkj5u4
Strome: Energy-Aware Data-Stream Processing
[chapter]
2018
Lecture Notes in Computer Science
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In contrast to DVFS, Strome exploits information on application performance and is therefore able to achieve energy savings while minimizing its effects on throughput and latency. ...
Our evaluation shows that Strome is particularly effective in the face of varying workloads, reducing power demand by up to 25 % compared with the state-of-the-art data-stream-processing system Heron relying ...
With inputs in many cases being related to user actions, the workload of a data-stream-processing system usually varies over time, often following diurnal patterns that are characteristic for data-center ...
doi:10.1007/978-3-319-93767-0_4
fatcat:hfjmlbqzl5cb7kc3q2wmcqm56q
A dynamic voltage scaled microprocessor system
2000
IEEE Journal of Solid-State Circuits
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The system consists of a dc-dc switching regulator, an ARM V4 microprocessor with a 16-kB cache, a bank of 64-kB SRAM ICs, and an I/O interface IC. ...
This provides a throughput range of 6-85 MIPS with an energy consumption of 0.54-5.6 mW/MIP yielding an effective energy efficiency as high as 26 200 MIPS/W. ...
The key design objective for the processor systems in these applications is to provide the highest possible peak throughput for the compute-intensive tasks while maximizing the battery life for the remaining ...
doi:10.1109/4.881202
fatcat:jfo3dxme25ckxegrlmv5chk5py
Modern Computer Architecture using different Technique
2021
International Journal of Computer Applications
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Current computer architecture research maintains a bias for the past in focuses to desktop and server application. ...
A distinct computer area, personal mobile computing, will, in my opinion, play a major role in propelling technology in the coming decade. ...
Data is transmitted between nodes in a NORMA machine at the request of an application (with a PUT or GET command). ...
doi:10.5120/ijca2021921751
fatcat:afsl7t5vunbabiaw3yku23hnau
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors
[article]
2021
arXiv
pre-print
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To operate efficiently across a wide range of workloads with varying power requirements, a modern processor applies different current management mechanisms, which briefly throttle instruction execution ...
Doing so 1) reduces the power consumption of non-PHI instructions in typical workloads and 2) optimizes system voltage regulators' cost and area for the common use case while limiting current consumption ...
integer, floating point, vector) and data widths (from 32 to 512 bits). 1 This large range of computational intensity across different instructions results in an instruction set with a wide range of ...
arXiv:2106.05050v2
fatcat:4z5c5vvbzbbbzgbpry6gldycr4
High-Performance Energy-Efficient Multicore Embedded Computing
2012
IEEE Transactions on Parallel and Distributed Systems
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high-performance embedded computing demands in an energy-efficient manner. ...
This paper outlines typical requirements of embedded applications and discusses state-of-the-art hardware/software high-performance energy-efficient embedded computing (HPEEC) techniques that help meeting ...
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSERC and the NSF. ...
doi:10.1109/tpds.2011.214
fatcat:vagqmojdsjevvc2u2ewqrcjjpq
Evaluating the power efficiency and performance of multi-core platforms using HEP workloads
2015
Journal of Physics, Conference Series
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On the other hand, the significant focus on power efficiency paves the way for power-aware computing and less complex architectures to data centers. ...
In this paper we try to examine these trends and present results of our experiments with Haswell-EP processor family and highly scalable HEP workloads. ...
This system might be considered outdated, but it is still run in the CERN Data Centre and in most sites of the WLCG (Worlwide LHC Computing Grid). ...
doi:10.1088/1742-6596/664/9/092024
fatcat:qiwqs5eww5ddnaknt6ow3nfoqq
A Heterogeneous Multi-core DSP Architecture for OFDM-Based Communication Systems
2016
International Journal of Future Generation Communication and Networking
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HeteroM-DSP consists of DSP cores based on VLIW instruction set architecture with good instruction set parallelism and data-level parallelism. ...
Meanwhile, in order to implement different OFDM systems flexibly, each DSP core has different computational capabilities. It is also improved processor performance/ power rate. ...
DSP cores adopt VLIW to coordinate with computer unit and memory control unit in implementing high instruction-level parallelism and data-level parallelism by executing multiple microinstructions within ...
doi:10.14257/ijfgcn.2016.9.10.28
fatcat:qwxcdthtpbepbakz5xy4oejc6y
Fault-Tolerant Computing with Heterogeneous Hardening Modes
[chapter]
2020
Embedded Systems
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This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories ...
like caches, for heterogeneous in-order and out-of-order processors. ...
We would like to thank Arun Subramaniyan, Duo Sun and Segnon Jean Bruno Ahandagbe for their contributions to parts of the works cited in this chapter. ...
doi:10.1007/978-3-030-52017-5_7
fatcat:d3wgo4fcvfcldgmhl2hfido5ee
Products & Materials
1986
Science
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The magnet is nestled in a cradle with the isolators forming the pivot point at a distance high above the center of mass of the whole system; this produces a mechanically passive system with a natural ...
processor or multiprocessors with only one intemal communications bus. ...
doi:10.1126/science.232.4758.1655
pmid:17812148
fatcat:5pp7pb4665h5nlmvwtuq6ck2om
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