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Harmless, a hardware architecture description language dedicated to real-time embedded system simulation

Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet
2012 Journal of systems architecture  
This paper presents Harmless 1 , a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems.  ...  Compared to existing ADLs, Harmless 1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse  ...  These languages are presented in section 2. This work presents Harmless (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new ADL.  ... 
doi:10.1016/j.sysarc.2012.05.001 fatcat:oyo7na2ckzbs5oi4vnor3ua4p4

Simulator generation using an automaton based pipeline model for timing analysis

Rola Kassem, Mikael Briday, Jean-Luc Bechennec, Yvon Trinquet, Guillaume Savaton
2008 International Multiconference on Computer Science and Information Technology  
This task can be alleviated by using a Hardware Architecture Description Language and generating the simulator.  ...  The description is transformed into an automaton and a set of resources which, in turn, are transformed into a simulator.  ...  A BRIEF DESCRIPTION OF HARMLESS The HARMLESS ADL allows to describe a hardware architecture using different parts: • the instruction set; • the hardware components used by the instructions like memory,  ... 
doi:10.1109/imcsit.2008.4747313 dblp:conf/imcsit/KassemBBTS08 fatcat:xhkc5y5km5hf5ghop36wxhs4ai

Formal Architecture Specification for Time Analysis [chapter]

Hajer Herbegue, Mamoun Filali, Hugues Cassé
2014 Lecture Notes in Computer Science  
First, we enhance the existing language Sim-nML for describing processors at the instruction level in order to capture modern architecture aspects.  ...  Second, we propose a light DSL in order to describe, in a formal prose, architectural aspects related to both the structural aspects as well as to the behavioral aspects.  ...  We have drawn a comparison between currently used description languages and formalism. In this paper we have used a processor model that possess real word processor features to test our approach.  ... 
doi:10.1007/978-3-319-04891-8_9 fatcat:lna4obnk3nhljozkhgazp53pym

BEST: a Binary Executable Slicing Tool

Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Marc Herbstritt
2016 Worst-Case Execution Time Analysis  
We describe the implementation of Best, a tool for slicing binary code. We aim to integrate this tool in a WCET estimation framework based on model checking.  ...  In this approach, program slicing is used to abstract the program model in order to reduce the state space of the system.  ...  Harmless is an Hardware Architecture Description Language that is used to model a whole processor. In this study, we are only interested in the model of the instruction set.  ... 
doi:10.4230/oasics.wcet.2016.7 dblp:conf/wcet/MangeanBBF16 fatcat:jak5mpflqnbz5dz6hlicos35nq

Exploring the Processor and ISA Design for Wireless Sensor Network Applications

Shashidhar Mysore, Banit Agrawal, Frederic T. Chong, Timothy Sherwood
2008 21st International Conference on VLSI Design (VLSID 2008)  
We then present a careful profiling of these benchmark applications using an ARM simulator to identify some of the key characteristic behaviors.  ...  On the other hand, a set of application-specific architectures have been proposed which perform certain operations extremely well but are not versatile enough to run a variety of applications.  ...  The main problem in the collection phase was to find the optimized code for one generic language instead of code written in a specialized language (such as nesC [6] ) or targeted for a very specific architecture  ... 
doi:10.1109/vlsi.2008.72 dblp:conf/vlsid/MysoreACS08 fatcat:osiy5fowirc2fekfnu7bt37lv4

Verilog Design of Programmable JTAG Controller for Digital VLSI IC's

Ramesh Bhakthavatchalu, Saranya K. Kannan, M. Nirmala Devi
2015 Indian Journal of Science and Technology  
All the designs were written in Verilog and RTL simulations were performed using Cadence NC-Sim Simulator. Cadence Encounter Test Architect 13.1 was used to check the boundary scan flow and analysis.  ...  The objective of this work is to design and implement a custom reconfigurable JTAG controller in Verilog. It can be directly inserted in to a new digital IC designs with little modifications.  ...  Similar to a logic design module a TAP controller can also be designs using a Hardware Description Language (HDL) .  ... 
doi:10.17485/ijst/2015/v8i17/62664 fatcat:6x6uglxmdjf2pjukffvdr4krym

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus (+13 others)
2002 IBM Journal of Research and Development  
PowerPC RISC architecture PowerPC [2] is traditionally recognized as a reducedinstruction-set computer (RISC) architecture which adheres to a basic philosophy of keeping the hardware design simple.  ...  Sim farm A massive simulation infrastructure was required to simulate a processor and system of this size and sophistication.  ...  Design modeling levels: M3 The hardware description language of choice for POWER4 was a subset of VHDL, the industry-standard HDL, and the primary choice in the IBM Server Group.  ... 
doi:10.1147/rd.461.0053 fatcat:474llttpkvghngwg4q6veuhvqq

0 Instruction Set Architecture [chapter]

2003 Digital Design and Computer Organization  
in a hardware description language, such as VHDL or Verilog, as well as, the generation of programming tools such as a C/C++ compiler or assembler, debugging and instruction-set simulation tools, and  ...  generate hardware RTL descriptions, an instruction-set simulator, a retargetable C compiler, and various other debugging and software development tools.  ...  slot --first ' strategy Listing A.8: Example exploration output using issue-slot first-match strategy 3 Found initial prototype mapped on : core_3b 4 Loading information from APEX file ... 5 Initial  ... 
doi:10.1201/b12403-15 fatcat:mygaz2meibgljew5tzvmuw6x5i

Dataflow machine architecture

Arthur H. Veen
1986 ACM Computing Surveys  
A general model for a dataflow machine is presented and the major design options are discussed.  ...  For general-purpose computing the most promising dataflow machines are those that employ packet-switching communication and support general recursion.  ...  The execution of a GENERATE-ACTIVA-TION-NAME instruction can be seen as the initiation of a new process.  ... 
doi:10.1145/27633.28055 fatcat:3tx3yxodkncunbnuzqoqrsngmm

A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures

Sandro Penolazzi, Ahmed Hemani, Luca Bolognino
2009 Journal of Low Power Electronics  
a trace of architectural transactions by actually simulating a model of architecture, usually in the form of an Instruction Set Simulator or a model of the hardware block.  ...  At the RT level, Hardware Description Language (HDL) languages are used to describe in words what RTL synthesis translates into logic gates.  ...  Figure 8 .8 is used as a reference during the algorithm description. Three independent tasks are shown, T 1 and T 3 being the highest and lowest priority task respectively.  ... 
doi:10.1166/jolpe.2009.1037 fatcat:rcs4t4wctvaw3pkhsdjp4fnvsm

Inferred designs

L. Perrochon, W. Mann
1999 IEEE Software  
Have you ever put a software system together without working out the full architecture before hand? If yes, did you feel guilty for not following good software practice?  ...  We introduce new methodologies to deal with rapid software evolution. However, we do not advocate eliminating the notion of design.  ...  The majority of existing architecture description languages do not support dynamic changes to the architecture.  ... 
doi:10.1109/52.795101 fatcat:yl4lvmpkofffxjrrdjldv3xkpy

Exposing vulnerabilities of untrusted computing platforms

Yier Jin, Michail Maniatakos, Yiorgos Makris
2012 2012 IEEE 30th International Conference on Computer Design (ICCD)  
This work seeks to expose the vulnerability of untrusted computing platforms used in critical systems to hardware Trojans and combined hardware/software attacks.  ...  5 encryption algorithm checking of a medium complexity micro-processor (8051).  ...  Hardware description language (HDL) codes for the 8051 core, the UART module, testbenches and simulation models were provided by NYU-Poly as part of the CSAW Embedded System Challenge [11].  ... 
doi:10.1109/iccd.2012.6378629 dblp:conf/iccd/JinMM12 fatcat:qlvdrencavhdfog5s2k3tbv34m

Extending programs with debug-related features, with application to hardware development [article]

Nik Sultana, Salvator Galea, David Greaves, Marcin Wojcik, Noa Zilberman, Richard Clegg, Luo Mai, Richard Mortier, Peter Pietzuch, Jon Crowcroft, Andrew W Moore
2017 arXiv   pre-print
We present a language of directing commands, specify its semantics in terms of a simple controller that is embedded with programs, and implement a prototype for directing network programs running in hardware  ...  This is done using ad hoc methods and primitive tools when compared to CPU programming. This complicates the programming and debugging of reconfigurable hardware.  ...  Matthew Grosvenor helped us with evaluation ideas and reusing the QJump infrastructure.  ... 
arXiv:1705.09902v1 fatcat:cr6yc7snozgq5bt3kcqgpz5jkq

Virtual Organization Clusters: Self-provisioned clouds on the grid

Michael A. Murphy, Sebastien Goasguen
2010 Future generations computer systems  
Virtual Organization Clusters (VOCs) provide a novel architecture for overlaying dedicated cluster systems on existing grid infrastructures.  ...  with hardware orders. iv April Bowen, Lea Benson, and Kim Keasler have generously provided their assistance with school and university policy compliance, fellowship administration, facilities support,  ...  By using virtual machines to run user jobs, the environment in which jobs execute becomes decoupled from the underlying hardware, allowing any physical site with a compatible Instruction Set Architecture  ... 
doi:10.1016/j.future.2010.02.011 fatcat:x6nwjn3c5jhnbfcuzeexdkz22a

Penetration Testing [chapter]

2014 Encyclopedia of Social Network Analysis and Mining  
It finds flaws in all the TCB evidence: policy, specification, architecture, assumptions, initial conditions, implementation, software, hardware, human interfaces, configuration control, operation, product  ...  The essay is largely based on the author's Flaw Hypothesis Methodology (FHM), the earliest and most widely used approach [WEIS73].  ...  The penetrators set up the bead attack by planting a breakpoint at a carefully prepared instruction on the same page as a string move command.  ... 
doi:10.1007/978-1-4614-6170-8_100424 fatcat:rnhgksdncvg5loxp3egznxiwua
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