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Instruction cache tuning for embedded multitasking applications
2010
IET Computers & Digital Techniques
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In this research work, we present novel, lightweight and fast techniques for energy-sensitive tuning of the instruction cache hierarchy for multitasking applications. ...
We then apply the proposed techniques to tune a predictor based filter cache hierarchy for instructions for both single-task based applications and RTOS-driven multitasking applications. ...
In this paper, we present a framework for energy centric-tuning of the instruction cache for embedded multitasking applications. ...
doi:10.1049/iet-cdt.2009.0066
fatcat:pmwfz5zqjzdpfihh7fosvsqkdu
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
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Data caches are often necessary to provide the required memory bandwidth. However, caches introduce two important problems for embedded systems. ...
Additionally, caches contribute to a significant amount of power. These issues are key factors for many embedded systems. ...
approach for real-time and energy-efficient embedded applications. ...
doi:10.1145/1289881.1289917
dblp:conf/cases/ReddyP07
fatcat:24zlovxkrfbbjnndewp4htfusa
A Survey of Embedded Software Profiling Methodologies
2011
International Journal of Embedded Systems and Applications
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It is achieved by profiling the application with variety of aspects like performance, memory usage, cache hit versus cache miss, energy consumption, etc. ...
Based on these observations, it will be easy to identify such common principles and needs which are required for a true Software Profiling Tool for a particular application. ...
Profilers customized for multitask applications, can also profile Operating System based applications. ...
doi:10.5121/ijesa.2011.1203
fatcat:vwf5plrtdzbdrdx25nz4gdsgce
On Using Locking Caches in Embedded Real-Time Systems
[chapter]
2005
Lecture Notes in Computer Science
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Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. ...
Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. ...
Embedded Real-Time Systems is a very exciting and expanding field, whose applications are found in command and control systems, process control, automated manufacturing. ...
doi:10.1007/11599555_17
fatcat:hfnqz5agk5dgpaz5gosy2hket4
2019 Index IEEE Computer Architecture Letters Vol. 18
2020
IEEE computer architecture letters
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-June 2019 55-58 Cache storage Code Layout Optimization for Near-Ideal Instruction Cache. ...
-June 2019 1-5
Encoding
Code Layout Optimization for Near-Ideal Instruction Cache. ...
Quantum computing Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. Zhou ...
doi:10.1109/lca.2020.2964168
fatcat:pv44gn35vrb75jabsid7x62xpm
SMP-SoC is the answer if you ask the right questions
2006
Proceedings of the 2006 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing couuntries - SAICSIT '06
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A case is made not only for designing a SMP-SoC alternative to the Cell, but for using such a design as an alternative to an aggressively-pipelined uniprocessor. ...
It makes a case for focusing design efforts on symmetric multiprocessor (SMP) SoC designs, which have the best chance of making an impact in a wide range of markets, rather than designs for very specific ...
Microprocessors, originally designed for simple embedded applications, have become the mainstream processor in conventional computers. ...
doi:10.1145/1216262.1216264
fatcat:xwnrcp5ncjfj7bacnljoyokmji
Throughput optimization via cache partitioning for embedded multiprocessors
2006
2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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In embedded multiprocessors cache partitioning is a known technique to eliminate inter-task cache conflicts, so to increase predictability. ...
For the H.264 application 9% throughput improvement is achieved when compared to the throughput obtained using methods of partitioning for the least number of misses. ...
Hence, the cache partitioning ratio is an important parameter that can be tuned to optimize the application performance. ...
doi:10.1109/icsamos.2006.300826
dblp:conf/samos/MolnosCHE06
fatcat:jdyarh5wz5gp5nafa3ktgfle4i
A survey of techniques for improving energy efficiency in embedded computing systems
2014
International Journal of Computer Aided Engineering and Technology
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In this paper, we survey the techniques for managing power consumption of embedded systems. ...
This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded ...
[89] present an approach for saving cache energy in multitasking embedded systems. ...
doi:10.1504/ijcaet.2014.065419
fatcat:r5kgr2rlnbaanca5mhgqwvicae
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems
2010
2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications
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Then, we extend Lock-MS to add support for hardware instruction prefetch. ...
Lock-MS is an ILP based method to obtain the best selection of memory lines to be locked in a dynamic locking instruction cache. ...
Specifically, for an instruction cache, the instruction fetch hits and misses depend on whether each instruction belongs to a cached and locked memory line and not on the previous accesses. ...
doi:10.1109/rtcsa.2010.8
dblp:conf/rtcsa/AparicioSRV10
fatcat:w4e4i74zxzdandccvvn44n52oq
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
[article]
2014
arXiv
pre-print
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In this paper, we survey the techniques for managing power consumption of embedded systems. ...
This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded ...
[89] present an approach for saving cache energy in multitasking embedded systems. ...
arXiv:1401.0765v1
fatcat:6lj7m34k6rcn3izdanqwfi35gu
Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded Multiprocessing
2009
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Snoop-induced cache lookups for accesses to the shared data are eliminated when it is ensured that such lookups will not result in extra knowledge regarding the cache state in respect to the other caches ...
snoop-induced cache lookups even for references to shared data, thus, achieving significant power reductions with minimal hardware cost. ...
EXPERIMENTAL RESULTS To evaluate the proposed technique, we have conducted detailed experiments on a set of embedded multitasking applications. ...
doi:10.1109/tvlsi.2009.2019414
fatcat:ghbec7zmsfb4bczvqeftj7vadi
Dynamic Cache Reconfiguration for Soft Real-Time Systems
2012
ACM Transactions on Embedded Computing Systems
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Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. ...
It is a major challenge to introduce cache reconfiguration into real-time multitasking systems since dynamic analysis may adversely affect tasks with timing constraints. ...
energy savings than application-based tuning. ...
doi:10.1145/2220336.2220340
fatcat:gdgovatdfnaorg7scliudjoa4y
Analysis of power dissipation in embedded systems using real-time operating systems
2003
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As a proof-of-concept, we use our infrastructure to produce the power profiles for a commercial RTOS, /OS-II, running several applications on an embedded system based on the Fujitsu SPARClite processor ...
This paper presents a method of producing a hierarchical energy-consumption profile for applications as they interact with an RTOS. ...
French, from NEC C&C Research Labs, for helpful discussions on real-time operating systems and his assistance with the Ethernet interface example. ...
doi:10.1109/tcad.2003.810745
fatcat:jujhtkyrsrcnbfa5b66jqht5mu
Frequent loop detection using efficient non-intrusive on-chip hardware
2003
Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03
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Our detector uses a tiny cache-like structure coupled with a small amount of logic. We provide results of extensive explorations across 19 embedded system benchmarks. ...
needed in timing-sensitive embedded systems. ...
A generic microprocessor with dynamic optimization capabilities can also tune itself to any application running on the microprocessor. ...
doi:10.1145/951710.951728
dblp:conf/cases/Gordon-RossV03
fatcat:ydudfednvndfvh2bnobujhmlsy
Frequent loop detection using efficient non-intrusive on-chip hardware
2003
Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03
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Our detector uses a tiny cache-like structure coupled with a small amount of logic. We provide results of extensive explorations across 19 embedded system benchmarks. ...
needed in timing-sensitive embedded systems. ...
A generic microprocessor with dynamic optimization capabilities can also tune itself to any application running on the microprocessor. ...
doi:10.1145/951727.951728
fatcat:fzlxz4bsrreqtkt5plaru6yyqy
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