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Modeling Power Dynamics for an Embedded DSP Processor Core [chapter]

C. H. Gebotys, R. Muresan
2002 IFIP Advances in Information and Communication Technology  
A new model for dynamic current analysis and simulation is presented for power and energy analysis of a complex VLIW DSP processor core, targeting secure wireless communications.  ...  For the first time results are verified with real power traces of a DSP processor core in a VLSI chip running cryptographic applications with an average error in energy estimation of 7%.  ...  This paper will present a methodology for modeling dynamic power simulation for a complex VLIW DSP processor core, the SC140.  ... 
doi:10.1007/978-0-387-35597-9_18 fatcat:7q6eq44dgrhcbazihkh6hd2leq

Current consumption dynamics at instruction and program level for a VLIW DSP processor

Radu Muresan, Catherine H. Gebotys
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
This paper describes a new methodology for analyzing lowlevel current dynamics at the instruction level and the program level for a VLIW DSP processor core.  ...  An efficient methodology for software power analysis is presented which unlike other research supports dynamic current analysis and complex VLIW processor cores.  ...  Since modeling power dissipation of a VLIW processor core is a very complex problem, new methods for tracing power dynamically at program levels and lower instruction levels are important.  ... 
doi:10.1145/500030.500032 fatcat:kgmwg2lduzc4xb4ypyng7rxc3y

Current consumption dynamics at instruction and program level for a VLIW DSP processor

Radu Muresan, Catherine H. Gebotys
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
This paper describes a new methodology for analyzing lowlevel current dynamics at the instruction level and the program level for a VLIW DSP processor core.  ...  An efficient methodology for software power analysis is presented which unlike other research supports dynamic current analysis and complex VLIW processor cores.  ...  Since modeling power dissipation of a VLIW processor core is a very complex problem, new methods for tracing power dynamically at program levels and lower instruction levels are important.  ... 
doi:10.1145/500001.500032 fatcat:4thmxqov5bcrph5n4ir7ao67x4

An instruction-level energy model for embedded VLIW architectures

M. Sami, D. Sciuto, C. Silvano, V. Zaccaria
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline, and its accuracy and efficiency has been compared with respect to energy estimates derived by gate-level  ...  In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information  ...  with a pipelined VLIW core.  ... 
doi:10.1109/tcad.2002.801105 fatcat:peio7clfmrftdjgkedejuh6rza

Power estimation methodology for VLIW Digital Signal Processors

Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy
2008 2008 42nd Asilomar Conference on Signals, Systems and Computers  
In this contribution the modeling of power consumption for the VLIW processor TMS320C6416T is presented taking into account typical software algorithms in signal and image processing.  ...  The modeling is performed at the functional level making this approach distinctly different from other modeling approaches in low level technique.  ...  Also they do not provide any insight on the instantaneous causes of power consumption within the processor core, which is seen as a black-box model. B.  ... 
doi:10.1109/acssc.2008.5074746 fatcat:q5dp7wwalnhsxf57mrjkma4m4i

A Precise High-Level Power Consumption Model for Embedded Systems Software

Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy
2011 EURASIP Journal on Embedded Systems  
In this paper, we present a precise high-level power estimation methodology for the software loaded on a VLIW processor that is based on a functional level power model.  ...  Third, we further validate the precision of our model on a real application applied in the video processing field.  ...  Acknowledgments This work has been funded by the Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms as well as the COMET K-Project Embedded Computer Vision (ECV) in conjunction  ... 
doi:10.1155/2011/480805 fatcat:ufwrxb27dfgf7epdjfy2hzbclu

A 90k gate "CLB" for Parallel Distributed Computing [chapter]

Bruce Schulman, Gerald Pechanek
2000 Lecture Notes in Computer Science  
In order to provide optimal algorithm performance, the VLIWs loaded to each PE configure that PE for processing. By reloading the local VLIW memories, each PE is reconfigured for a new algorithm.  ...  This distributed processor uses a lowcost interconnection network and local indirect VLIW memories to provide efficient algorithm implementations for portable battery operated products.  ...  Depending upon the size of the VLIW memory and the number of VLIWs needed for each algorithm in an application, the optimized set of VLIWs for multiple tasks can be resident in the VIM, allowing instantaneous  ... 
doi:10.1007/3-540-45591-4_114 fatcat:hku55mtay5dxbieqqe6z2upd34

Android Based Energy Aware Framework for Porting Legacy Applications

Naeem Zafar Azeemi
2014 American Journal of Applied Sciences  
The impact of TSF is discussed for different multimedia applications in native Digital Signal Processor (DSP) compiler optimization while switching between different transformation schemes.  ...  Trend is growing towards using complex multimedia functions on smaller devices.  ...  ., 2000) tried to model the complex energy behavior of VLIW processors.  ... 
doi:10.3844/ajassp.2014.1980.1987 fatcat:cpkbkosflnfk5piokvug6mrofe

Power Aware Framework for Dense Matrix Operations in Multimedia Processors

N. Zafar Azeemi
2005 2005 Pakistan Section Multitopic Conference  
The approach is illustrated using functional unit usage within a VLIW architecture for low power, which improves energy dissipation up to 34% and CPU performance up to 87% for an idct example.  ...  In this paper we analyze 1 the use of Decision Tree Grafting, Blocking and Loop Unfolding to improve the performance of dense matrix computations on high performance multimedia processors.  ...  Some researcher [16, 18, 19] tried to model the complex energy behavior of processors in terms of usage of their various functional units, mainly targeted for VLIW.  ... 
doi:10.1109/inmic.2005.334414 fatcat:pzmkdxwzx5a5flh4kczmsxv5za

A loop accelerator for low power embedded VLIW processors

Binu Mathew, Al Davis
2004 Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04  
The idea is evaluated in the context of a fine grain VLIW architecture executing complex perception algorithms such as speech and visual feature recognition.  ...  A distributed address generation and loop acceleration architecture for VLIW processors is presented.  ...  ARCHITECTURE The loop acceleration technique will be evaluated on two processor configurations, a VLIW integer core and a VLIW floating point core both of which follow the generic organization shown in  ... 
doi:10.1145/1016720.1016726 dblp:conf/codes/MathewD04 fatcat:fcnyomdcofgdhjvhhrs2chebri

IEEE 802.11AC MIMO transmitter baseband processing on customized VLIW processor

Mona Aghababaeetafreshi, Lasse Lehtonen, Maliheh Soleimani, Mikko Valkama, Jarmo Takala
2014 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
This paper presents a software-based implementation for the MIMO transmitter baseband processing conforming to the IEEE802.11ac standard on a DSP core with vector extensions.  ...  The proposed software solution is evaluated in terms of power consumption, number of clock cycles and memory usage.  ...  This DSP core is a 4-issue VLIW processor and has support for vector operations with the aid of a 16-way SIMD ALU engine and 32-way MAC SIMD engine.  ... 
doi:10.1109/icassp.2014.6855058 dblp:conf/icassp/AghababaeetafreshiLSVT14 fatcat:vteugfbg5ffnnjuzzevqnqln64

A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System

Haifeng Zhang, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang, Shengbing Zhang
2021 Sensors  
Unfortunately, the general micro-controller-class processors which are widely used in sensing system fail to achieve real-time inference.  ...  In this paper, we proposed a lightweight pipeline integrated deep learning architecture, which is compatible with open-source RISC-V instructions.  ...  Acknowledgments: We thank Hui Qiang, Xin Li and Jiaying Yang for their assistance in providing the experimental data. Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s21196491 pmid:34640811 fatcat:mbr2d5mggrhhje24dvgdzo4yqu

A Manycore Vision Processor for Real-Time Smart Cameras

Bruno A. da Silva, Arthur M. Lima, Janier Arias-Garcia, Michael Huebner, Jones Yudi
2021 Sensors  
In this work, we show the design and implementation of a manycore vision processor architecture to be used in Smart Cameras.  ...  Using a System-on-Chip composed of an FPGA integrated into a general-purpose processor, we showcase the flexibility and efficiency of the hardware/software architecture.  ...  VLIW processors can perform several operations in parallel, offering a suitable approach.  ... 
doi:10.3390/s21217137 pmid:34770444 pmcid:PMC8587860 fatcat:uf45ud4v6fdmdj3chrz5vcsi7y

Instruction scheduling for VLIW processors under variation scenario

Nayan V. Mujadiya
2009 2009 International Symposium on Systems, Architectures, Modeling, and Simulation  
In Very Long Instruction Word (VLIW) processors, based on the available instruction-level parallelism in programs, compilers schedule operations onto different functional units.  ...  Process variations in components like adders, multipliers, etc., of different Integer Functional Units (IFUs) in VLIW processors may cause these units to operate at different speeds, resulting in non-uniform  ...  A VLIW compiler reads a program written in a high level programming language and translates the complex operations into micro operations that are supported by the processor.  ... 
doi:10.1109/icsamos.2009.5289239 dblp:conf/samos/Mujadiya09 fatcat:ufevv3cs5beixbqvvj647juybe

Dynamic Current Modeling at the Instruction Level

Jose Rizo-Morente, Miguel Casas-Sanchez, C.J. Bleakley
2006 ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design  
The method models dynamic current as the output of a linear system excited by a signal comprised of the total current due to each instruction.  ...  Estimation of processor current consumption is important for the design of low power systems. This paper proposes a novel method for estimating the dynamic current consumption of a processor.  ...  A number of architectures have been modelled using FLPA. In particular, those with large numbers of functional units operating in parallel, such as Very Long Instruction Word (VLIW) processors.  ... 
doi:10.1109/lpe.2006.4271814 fatcat:fyawsewzevevni2sbyo2x342ua
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