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Inherent limitations of hybrid transactional memory

Dan Alistarh, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, Nir Shavit
2017 Distributed computing  
Hybrid transactional memory model Our baseline model for transactional memory systems is the standard software TM model [11] .  ...  Several Hybrid Transactional Memory (HyTM) schemes [4, 6, 14, 15] have been proposed to complement the fast, but best-effort nature of HTM with a slow, reliable software transactional memory (STM) backup  ... 
doi:10.1007/s00446-017-0305-3 fatcat:odg2m3ikzzg3hazw4svhy2o3aa

Inherent Limitations of Hybrid Transactional Memory [article]

Dan Alistarh, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, Nir Shavit
2015 arXiv   pre-print
Several Hybrid Transactional Memory (HyTM) schemes have recently been proposed to complement the fast, but best-effort, nature of Hardware Transactional Memory (HTM) with a slow, reliable software backup  ...  However, the fundamental limitations of building a HyTM with nontrivial concurrency between hardware and software transactions are still not well understood.  ...  Introduction Hybrid transactional memory.  ... 
arXiv:1405.5689v3 fatcat:stdkilpqmfhg3gi4zxog4wqeh4

Inherent Limitations of Hybrid Transactional Memory [chapter]

Dan Alistarh, Justin Kopinsky, Petr Kuznetsov, Srivatsan Ravi, Nir Shavit
2015 Lecture Notes in Computer Science  
Hybrid transactional memory model Our baseline model for transactional memory systems is the standard software TM model [11] .  ...  Several Hybrid Transactional Memory (HyTM) schemes [4, 6, 14, 15] have been proposed to complement the fast, but best-effort nature of HTM with a slow, reliable software transactional memory (STM) backup  ... 
doi:10.1007/978-3-662-48653-5_13 fatcat:mc2wdxbumfh3homcjepsjlpghm

DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs [article]

Mohammad Qayum and Abdel-Hameed Badawy and Jeanine Cook
2017 arXiv   pre-print
One of the solutions is to format the data as graph data structures and process them on shared memory architecture to use fast and novel policies such as transactional memory.  ...  Due to this sparsity, we have the opportunity to use Transactional Memory (TM) as the synchronization policy for critical sections to speedup applications.  ...  Hybrid Transactional Memory (HyTM) scheme optimizes the combination of Software Transactional Memory (STM) and Hardware Transactional Memory (HTM) depending on the requirement of the application [12]  ... 
arXiv:1702.07081v2 fatcat:kub4v3jn25gizdzdurpca7kaou

Brief Announcement

Mohamed Mohamedin, Roberto Palmieri, Ahmed Hassan, Binoy Ravindran
2015 Proceedings of the 27th ACM on Symposium on Parallelism in Algorithms and Architectures - SPAA '15  
In this paper we present Part-HTM, the first hybrid transactional memory protocol that solves the problem of transactions aborted due to the resource limitations (space/time) of current best-effort HTM  ...  The first release of hardware transactional memory (HTM) as commodity processor posed the question of how to efficiently handle its best-effort nature.  ...  While acknowledging the importance of an opaque hybrid-TM protocol, in this paper we briefly introduce two versions of Part-htm.  ... 
doi:10.1145/2755573.2755611 dblp:conf/spaa/MohamedinPHR15 fatcat:o7lhgzqynnet7hmkc7ffbgp3j4

An iterative current-based hybrid method for complex structures

R.E. Hodges, Y. Rahmat-Samii
1997 IEEE Transactions on Antennas and Propagation  
Traditional method of moments (MoM) analysis is inherently limited to electrically small and moderately large electromagnetic structures, because its computation costs (in terms of memory and CPU time)  ...  Theoretical foundation of the hybrid technique is a system of coupled surface integral equations, with an electric field integral equation (EFIE) in the exact (MoM) part of the structure under consideration  ... 
doi:10.1109/8.560345 fatcat:6p7fbom6obcz5ab56lariljjx4

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

T.D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Yuan Xie, C. Das, V. Degalahal
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
Both implementations have some inherent disadvantages -the former resulting from poor scalability and the transactional character of their operation, and the latter from inconsistent access times and deterioration  ...  In order to exploit the advantages of the dTDMA bus for smaller configurations, and the scalability of NoC's, we propose a new hybrid SoC interconnect combining the two, showing significant improvement  ...  Furthermore, traditional bus architectures such as AMBA [1] and CoreConnect [13] have inherent disadvantages when applied to SoC's resulting from their transactional model of operation.  ... 
doi:10.1109/vlsid.2006.10 dblp:conf/vlsid/RichardsonNPVXDD06 fatcat:yy7f33ek2bgi3mgxframlxg24e

Hybrid NOrec

Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear
2011 SIGPLAN notices  
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors.  ...  We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware  ...  Acknowledgments Our thanks to Dave Dice for his implementation of NOrec STM, to Dan Nussbaum for his initial integration of NOrec into Oracle's SkySTM hybrid infrastructure, to Stephan Diestelhorst for  ... 
doi:10.1145/1961296.1950373 fatcat:g7hlngayw5ft3iatyr2y5cudpe

Hybrid NOrec

Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear
2011 SIGARCH Computer Architecture News  
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors.  ...  We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware  ...  Acknowledgments Our thanks to Dave Dice for his implementation of NOrec STM, to Dan Nussbaum for his initial integration of NOrec into Oracle's SkySTM hybrid infrastructure, to Stephan Diestelhorst for  ... 
doi:10.1145/1961295.1950373 fatcat:va4bt6smwvapnatou3kru5fogm

Hybrid NOrec

Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear
2012 SIGPLAN notices  
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors.  ...  We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware  ...  Acknowledgments Our thanks to Dave Dice for his implementation of NOrec STM, to Dan Nussbaum for his initial integration of NOrec into Oracle's SkySTM hybrid infrastructure, to Stephan Diestelhorst for  ... 
doi:10.1145/2248487.1950373 fatcat:cqnzkcc3ybfj3fmclvknoxdnyy

Hybrid NOrec

Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear
2011 Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems - ASPLOS '11  
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors.  ...  We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware  ...  Acknowledgments Our thanks to Dave Dice for his implementation of NOrec STM, to Dan Nussbaum for his initial integration of NOrec into Oracle's SkySTM hybrid infrastructure, to Stephan Diestelhorst for  ... 
doi:10.1145/1950365.1950373 dblp:conf/asplos/DalessandroCWLMSS11 fatcat:ucaodjswynathicmjcd4hqgwra

Preventing session hijacking in collaborative applications with hybrid cache-supported one-way hash chains

Amerah Alabrah
2014 Proceedings of the 10th IEEE International Conference on Collaborative Computing: Networking, Applications and Worksharing  
We also evaluate the hybrid scheme with simulation experiments of different configurations and scenarios.  ...  The results of the simulation experiments show that the hybrid scheme improves performance of the OHC tremendously while efficiently and securely handling authentication.  ...  We propose a hybrid solution that maximizes efficiency and minimizes the cost of memory resources.  ... 
doi:10.4108/icst.collaboratecom.2014.257327 dblp:conf/colcom/AlabrahB14 fatcat:762ztgns4fdt7di6spfeaiwkje

A Novel Idea on Multimedia Encryption Using Hybrid Crypto Approach

Sridhar C. Iyer, R.R. Sedamkar, Shiwani Gupta
2016 Procedia Computer Science  
This paper mainly focusses on the implementation of a system capable of encryption and decryption of multimedia data (Text, Images, Videos, Audio etc.) using a hybrid model based on the amalgamation of  ...  Even if the attacker gets access to any of the keys, he or she won't be in a position to decipher it in a relatively finite amount of man-years.  ...  RSA is really helpful for providing security to online transactions and highly confidential transactions over a network but has some inherent limitations as well.  ... 
doi:10.1016/j.procs.2016.03.038 fatcat:wopq4njworejfjcr4hpxbcaihe

A survey on optimizations towards best-effort hardware transactional memory

Zhenwei Wu, Kai Lu, Ruibo Wang, Wenzhe Zhang
2020 CCF Transactions on High Performance Computing  
Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as  ...  There has been a large number of discussions towards transactional memory systems, which aimed at providing relatively simple and intuitive synchronization construction for shared-memory parallel programs  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their valuable comments and suggestions to improve the quality of the paper.  ... 
doi:10.1007/s42514-020-00049-2 fatcat:lf5s3agulfhpzgxcjgjk2msqfy

Memory system architecture for the data centric computing

Ken Takeuchi
2016 Japanese Journal of Applied Physics  
random access memory (PRAM) hybrid memory system for the big-data applications.  ...  Thus, the key challenge is to reduce the cost of moving data through the deep memory hierarchy from the storage through the main memory to the CPU and eventually to resolve the Von Neumann bottleneck.  ...  Comprehensive comparison of the hybrid SSD and all SCM SSD was originally published in Refs. 28 and 29.  ... 
doi:10.7567/jjap.55.04ea02 fatcat:wqrsaavh3ja23cxq4oidnolam4
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