A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
Incremental compilation for logic emulation
Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)
Preserved Fulltext
In this paper we describe and analyze a set of incremental compilation steps, including incremental design partitioning and incremental inter-FPGA routing, for two specific classes of multi-FPGA emulation ...
As system sizes and design compilation times increase, the need to support rapid, incremental compilation grows progressively important. ...
Conclusions and Future Work In this paper incremental design compilation for multi-FPGA logic emulation systems has been evaluated through the use of new algorithms for incremental partitioning and routing ...
doi:10.1109/iwrsp.1999.779059
dblp:conf/rsp/Tessier99
fatcat:moe5xsjwwncetp5h3nbu3bcvjq
Incremental compilation for parallel logic verification systems
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2003; you can also visit the original URL.
The file type is application/pdf.
In this paper, we describe and analyze a set of incremental compilation steps that can be directly applied to a range of parallel logic verification hardware, including logic emulators. ...
To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator [ ...
To prove the benefit of the incremental design approaches, we have targeted incremental compilation techniques to an FPGAbased logic emulation system available from Ikos Systems [1] . ...
doi:10.1109/tvlsi.2002.801614
fatcat:r6l3cna55zbsvc2jcnrj7bhiju
Page 4 of Hewlett-Packard Journal Vol. 34, Issue 3
[page]
1983
Hewlett-Packard Journal
Preserved Fulltext
The Internet Archive has digitized a microfilm copy of this work. It may be possible to borrow a copy for reading.
The addition of emulator options with up to one megabyte of independent memory in 32K, 64K, or 128K-byte increments gives the user an executing and debugging environment and a tool for integrating
4 HEWLETT-PACKARD ...
Both Pascal and C cross-compilers are available for a number of micro- processors, and a host Pascal compiler is available to exe- cute on the 64000 System. ...
A heterogeneous computer vision architecture: Implementation issues
1995
Computing Systems in Engineering
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
development tools containing a structured editor--syntax oriented, with a visual interface/programming interface--and a cross compiler and debugger. ...
The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level--transputer based--and on VLSI associative processor arrays (APA, SIMD structure) for ...
Acknowledgements The authors wish to acknowledge the financial support of the Junta Nacional de Investiga~;~o Cientifica Nacional (JNICT), Portugal, for this work. ...
doi:10.1016/0956-0521(95)00029-1
fatcat:oszogta3mzarzceerbzrlv3wbi
The interpreter
1971
Proceedings of the November 16-18, 1971, fall joint computer conference on - AFIPS '71 (Fall)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The one path involves the standard compilation process followed by an emulation and the other path involves interpretation. Compilation consists of two basic functions: Analysis and Synthesis. ...
The Analysis is basically the same as that described above for the compilation process. ...
, 1, 2, 3 address) including effective operand address calculation, and 3. operation codes and their functional meaning (instructions for arithmetic, branching, etc.). ...
doi:10.1145/1478873.1478965
dblp:conf/afips/ReigelFF72
fatcat:ik3cag6re5dphlph5nfp56npjy
RTL emulation
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The worldwide electronics market is booming, fueled by the customers' insatiable appetite for low-cost computers, connectivity and appliances packed with high-technology features. ...
The core emulation software includes a partitioner, compiler, and a suite of diagnostics. ...
An incremental synthesis process enables fast iterative changes to a design. An incremental synthesis is closely coupled with source level EOO. ...
doi:10.1145/240518.240561
dblp:conf/dac/SawantG96
fatcat:v4u2ulud3vdwrhoxi23rwageba
Benu: Operating System Increments for Embedded Systems Engineer's Education
2014
Proceedings of the 2014 Federated Conference on Computer Science and Information Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Each increment builds on the previous one and introduces new system elements, new concepts and solutions, and a new set of assignments for improving or extending operations or simply demonstrating its ...
This paper presents a new incrementally built operating system and a learning course formed around it. ...
Compiling programs using logical addresses complicates the building process. ...
doi:10.15439/2014f237
dblp:conf/fedcsis/JelenkovicJG14
fatcat:hwpobu6djvcd7e5w7yykknv2yu
Riker Evaluation Guide for ATC '22 Artifact Evaluators
[article]
2022
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
This software artifact includes the Riker build system, results for the paper accepted at USENIX ATC'22, and instructions on how to reproduce the results from the paper for the purposes of artifact evaluation ...
This is because sqlite's build concatenates all of its source files together before compiling them. No incremental compilation is possible. ...
With RIKER's compiler wrapper, simple lines like gcc *.c start parallel compilation tasks for each source file, which RIKER can also run in parallel for later rebuilds. ...
doi:10.5281/zenodo.6544917
fatcat:e6k3h4izuzdy7l7qwdaoglcpua
LaForge: Always-Correct and Fast Incremental Builds from Simple Specifications
[article]
2021
arXiv
pre-print
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Other Versions
LaForge's incremental builds consistently run fewer commands, and most take less than 3.08s longer than manually-specified incremental builds. Finally, LaForge is always correct. ...
Simple build specifications are easy to write, but limit incremental work. More complex build specifications produce faster incremental builds, but writing them is labor-intensive and error-prone. ...
Dependency generation is only available for compilers with explicit make support, and still it requires that users manually insert incremental build targets. ...
arXiv:2108.12469v2
fatcat:ubxyanlgxzevzgxgevketjverm
Logic emulation with virtual wires
1997
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
He was a founder of Virtual Machine Works, Inc., which was aimed at productizing the VirtualWires technology for logic emulation. ...
Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. ...
We measured emulation logic resource consumption by compiling unvirtualized partitions onto high-pin-count FPGA's. ...
doi:10.1109/43.640619
fatcat:xslresgiivbi7pjbujhtecivii
Logic Emulation with Virtual Wires Manuscript received March 20, 1995; revised April 26, 1996 and June 17, 1997. This work was supported by ARPA Contract N00014-91-J-1698 and NSF Grant MIP-9012773. This paper was recommended by Associate Editor C.-K. Cheng. Publisher Item Identifier S 0278-0070(97)07006-1
[chapter]
2002
Readings in Hardware/Software Co-Design
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
He was a founder of Virtual Machine Works, Inc., which was aimed at productizing the VirtualWires technology for logic emulation. ...
Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. ...
We measured emulation logic resource consumption by compiling unvirtualized partitions onto high-pin-count FPGA's. ...
doi:10.1016/b978-155860702-6/50058-2
fatcat:z7simtmezreitcvsypfzt2yf6e
DEEP
2011
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
This platform exhibits the following three characteristics: fast compilation of logic designs, debugging support, and affordability. ...
It is based on a novel iterative emulation methodology for hardware design and verification. ...
We run the benchmark on the emulation system for problem sizes starting at 16x16 at increments of 16 up to the maximum supported problem size of 512x512 elements. ...
doi:10.1145/1950413.1950438
dblp:conf/fpga/RibutzkaHCG11
fatcat:nmm5lsw5i5e6jgzv32m656krwq
Static scheduling of multidomain circuits for fast functional verification
2002
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
To prove the effectiveness of the authors' approach, developed algorithms have been integrated into the compilation system for a commercial multi-FPGA logic emulation system. ...
For three designs mapped to a logic emulator using this software environment, modeling fidelity is maintained and performance is enhanced versus previous manual mapping approaches. ...
The approach has been demonstrated on a VirtuaLogic emulation system for three large commercial benchmark designs. The algorithms were integrated into a commercial compiler for logic emulation. ...
doi:10.1109/tcad.2002.804086
fatcat:owoc5agfwjg5nicdstivbbnw3y
DBToaster
2009
Proceedings of the VLDB Endowment
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf.
We present DBToaster, a novel query compilation framework for producing high performance compiled query executors that incrementally and continuously answer standing aggregate queries using in-memory views ...
C++ functions for evaluating database updates (deltas). ...
order book data [2], and emulating a combined data warehouse loading and analysis application for TPC-H data. ...
doi:10.14778/1687553.1687592
fatcat:yuclkhzinba2njh7cwf4fy4a5e
Fast Query Evaluation with (Lazy) Control Flow Compilation
[chapter]
2004
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2006; you can also visit the original URL.
The file type is application/pdf.
This improves performance in two ways: it opens the way to incremental compilation of the generated queries, and also gives potentially large gains by never compiling dynamically unreachable code. ...
Because these queries are executed often, the trade-off between meta-calling and compiling & running them has been in favor of the latter, as compiled code is faster. ...
We are indebted to Bart Demoen for his significant contributions to the achievements presented in this paper. ...
doi:10.1007/978-3-540-27775-0_17
fatcat:7jmz7kiirzepjfqfu3ihhu75gi
« Previous
Showing results 1 — 15 out of 9,891 results