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Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Yongjun Park, Jason Jong Kyu Park, Hyunchul Park, Scott Mahlke
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
However, the energy budgets are increasing at a much lower rate, requiring fundamental improvements in computing efficiency.  ...  The Libra accelerator increases SIMD utility by blurring the divide between vector and instruction parallelism to support efficient execution of a wider range of loops, and it increases hardware utilization  ...  Dynamic configurability enables lane resource to execute as a traditional SIMD processor, be re-purposed to behave as a clustered VLIW processor, or combinations in between.  ... 
doi:10.1109/micro.2012.17 dblp:conf/micro/ParkPPM12 fatcat:3skvsbe2vbeujmh2ctwoqwmthe

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei
2019 ACM Computing Surveys  
As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia  ...  However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability.  ...  Some CGRAs, such as TIA and TRIPS, could be used as a parallel computing processor that is equal to a CPU in an operating system.  ... 
doi:10.1145/3357375 fatcat:pqi4d33i6bg45a6llswhwd44qi

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

Sparsh Mittal
2016 ACM Computing Surveys  
In this paper, we present a survey of architectural and system-level techniques proposed for designing and managing AMPs.  ...  We clarify the terminology used in this research field and identify challenges that are worthy of future investigation.  ...  Based on this, they propose a design that uses OOO, VLIW and InO execution backends in each core.  ... 
doi:10.1145/2856125 fatcat:3hda47vtl5fznfvbskwcm2cbo4

Hybrid Dataflow/von-Neumann Architectures

Fahimeh Yazdanpanah, Carlos Alvarez-Martinez, Daniel Jimenez-Gonzalez, Yoav Etsion
2014 IEEE Transactions on Parallel and Distributed Systems  
In this paper, we classify hybrid dataflow/von-Neumann models according to two different taxonomies: one based on the execution model used for inter-and intrablock execution, and the other based on the  ...  Finally, we compare a representative set of recent general purpose hybrid dataflow/von-Neumann architectures, discuss their different approaches, and explore the evolution of these hybrid processors.  ...  resource utilization.  ... 
doi:10.1109/tpds.2013.125 fatcat:rswr6zvvjjamxjjca6p2cfhh5y

Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor

K.s. Tham, D.L. Maskell
2006 2006 International Conference on Field Programmable Logic and Applications  
Recent advancements in mixed hardware-software modeling platforms have shown great potential in providing the use of a common software language for describing the hardware and software of the entire system  ...  Innovative embedded applications like video and internet streaming in the multimedia domain have greatly increased the computational workload of embedded systems in consumer products.  ...  FCCM has a dynamic hardware resource utilization compared to coarse-grained types where the resource model is static.  ... 
doi:10.1109/fpl.2006.311230 dblp:conf/fpl/ThamM06 fatcat:jyvrwl33uzcytolxwgywctvmwm

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
2020 IEEE Access  
Recently, a particular branch of reconfigurable architecture -the Field-Programmable Gate Arrays (FPGAs) [9] -has experienced a surge of renewed interest for use in High-Performance Computing (HPC), and  ...  Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between  ...  This article is based on results obtained from a project commissioned by New Energy and Industrial Technology Development Organization (NEDO).  ... 
doi:10.1109/access.2020.3012084 fatcat:xx6k4lxbjbc4tjebbymp42w634

A secure isolation of software activities in tiny scale systems

Oliver Stecklina
2015 2015 IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops)  
The lack of resource isolation makes tiny scale systems prone for accidental errors but in particular vulnerable for a broad variety of malicious software.  ...  For a safe and secure operation of computer systems it is strongly recommended that software components are isolated in such a manner that they have access only to those resources, which are assigned to  ...  When using 32 DDT entries the overall resource utilization is 270 % in comparison to the utilization of the tinyVLIW8 soft-core processor.  ... 
doi:10.1109/percomw.2015.7134037 dblp:conf/percom/Stecklina15 fatcat:exjpv5kxrzgczimh2rwjabeere

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective [article]

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
2020 arXiv   pre-print
Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between  ...  In this paper, we survey the landscape of CGRAs.  ...  ACKNOWLEDGEMENTS This article is based on results obtained from a project commissioned by the New energy and Industrial Technology Development Organization (NEDO).  ... 
arXiv:2004.04509v1 fatcat:sxnq32chxjf6hfc5ygjsxqjwl4

Chip multi-processor generator

Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
2007 Proceedings - Design Automation Conference  
The amount of resources in a programmable platform (e.g., compute engines, instruction and data caches, processor width, memory bandwidth, etc.) is never optimal for any particular application.  ...  For example, many applications within a domain may require similar systems with small variations in hardware units, or the same application may be used in multiple target devices with different power and  ...  Devices with coarse-grain programmability, such as SDR baseband processors, must find compromises in the mix of hardware resources that are put on the die.  ... 
doi:10.1145/1278480.1278544 dblp:conf/dac/SolomatnikovFQSKAWHH07 fatcat:r5cfnoxqarg5lghtnmqidi7wxy

Techniques for obtaining high performance in Java programs

Iffat H. Kazi, Howard H. Chen, Berdenia Stanley, David J. Lilja
2000 ACM Computing Surveys  
Another alternative for executing Java programs is a Java processor that implements the JVM directly in hardware.  ...  Various types of Java compilers have been proposed, including Just-In-Time (JIT) compilers that compile bytecodes into native processor instructions on the fly; direct compilers that directly translate  ...  ACKNOWLEDGMENTS We thank Amit Verma and Shakti Davis for their help in gathering some of the information used in this paper.  ... 
doi:10.1145/367701.367714 fatcat:76fvbgkvnffodgpip2lhajvz4m

06141 Abstracts Collection – Dynamically Reconfigurable Architectures

Jürgen Becker, Jürgen Teich, Gordon Brebner, Peter M. Athanas
Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper.  ...  The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.  ...  In particular for coarse-grained recongurable architectures, a designer must consider how each application makes use of the provided architectural resources.  ... 
doi:10.4230/dagsemproc.06141.1 fatcat:r7k4pmvsdrdvne5sa3cyr4okfy

PSciLab: An Unified Distributed and Parallel Software Framework for Data Analysis, Simulation and Machine Learning—Design Practice, Software Architecture, and User Experience

Stefan Bosse
2022 Applied Sciences  
In this paper, a hybrid distributed-parallel cluster software framework for heterogeneous computer networks is introduced that supports simulation, data analysis, and machine learning (ML), using widely  ...  about parallel and distributed systems and their interaction.  ...  state machine (FSM)) in a cell of a cellular automata (CA) system or a more complex agent in a multi-agent system (MAS).  ... 
doi:10.3390/app12062887 fatcat:2prgkzfnvfdxbgwrwg2iq55um4

Vector processing as a soft-core processor accelerator

Jason Kwok Kwun Yu
The soft vector processor can be further customized by a number of secondary parameters to add and remove features for the specific application to optimize resource utilization.  ...  Soft processors simplify hardware design by being able to implement complex control strategies using software.  ...  VLIW Processors VLIW architectures have also been used in FPGAs for acceleration.  ... 
doi:10.14288/1.0066643 fatcat:j3bzq5oo4zf6xpzx5rpr2i5dwm

Università degli Studi di Bologna Software Tools for Embedded Reconfigurable Processors Tesi di Dottorato di Relatore Reconfigurable architectures Programming environment Application Development HW/SW Co-Design Digital Signal Processing

Facolt` Facolt`a, D Facolt`a, Ingegneria, Claudio Mucci, Chiar Mo, Guerrieri Roberto, Chiar Coordinatore, Paolo Mo, Bassi
2005 unpublished
Conclusions Appendix A Griffy-C syntax 66 . Griffy  ...  overhead in the resources utilization.  ...  spread the computation over a mix of processor and configware resources, and configuration tools often discard kernels with strange operators.  ... 


Davide Rossi
The MOLEN polymorphic processor [12] couples a general-purpose processor with a reconfigurable co-processor enhanced with hardware facilities for synchronization and arbitration as shown in Figure 1  ...  On the other hand, the applications and platforms used in many of today's system designs are based on heterogeneous Multi-Processor System-On-Chip (MPSoCs).  ... 
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