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Continual Learning Approach for Improving the Data and Computation Mapping in Near-Memory Processing System [article]

Pritam Majumder, Jiayi Huang, Sungkeun Kim, Abdullah Muzahid, Dylan Siegers, Chia-Che Tsai, Eun Jung Kim
2021 arXiv   pre-print
The resurgence of near-memory processing (NMP) with the advent of big data has shifted the computation paradigm from processor-centric to memory-centric computing.  ...  To meet the bandwidth and capacity demands of memory-centric computing, 3D memory has been adopted to form a scalable memory-cube network.  ...  (iv) Near compute remapping: remap the compute location to one of the current compute cube's neighbors.  ... 
arXiv:2104.13671v1 fatcat:fe2slbojkndufibfikgxpajqqe

Special Issue on In-Memory Computing

Reetuparna Das
2022 IEEE Micro  
In-/near-memory computing paradigm blurs this distinction and imposes the dual responsibility on memory substrates: storing and computing on data.  ...  In-/near-memory processing converts these memory units into powerful allies for massively parallel computing, which can accelerate a plethora of applications including neural networks, graph processing  ...  THE IEEE MICRO SPECIAL ISSUE ON IN-MEMORY COMPUTING WILL EXPLORE ACADEMIC AND INDUSTRIAL RESEARCH ON TOPICS THAT RELATE TO IN-/NEAR-MEMORY COMPUTING.  ... 
doi:10.1109/mm.2021.3137536 fatcat:lsgvtuatjzdnzny6uwvty3wwhy

Trading Computation for Communication: A Taxonomy [article]

Ismail Akturk, Ulya R. Karpuzcu
2017 arXiv   pre-print
., computation), (re)computing data can easily become cheaper than storing and retrieving (pre)computed data.  ...  This paper hence provides a taxonomy for the computation vs. communication trade-off along with quantitative characterization.  ...  Processing in/near memory [28, 18, 25, 14, 19] can bridge the gap between logic and memory speeds by embedding compute capability in/near memory.  ... 
arXiv:1709.06555v1 fatcat:n3rinehh75dmppd63wkihbujxq

Table of Contents

2021 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)  
Jones (University of Cambridge, UK) Session 4A: Processing in/near Memory ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-Based Near-Memory Processing with Inter-DIMM Broadcast 237 Weiyi  ...  Tsinghua University, China), and Leibo Liu (Tsinghua University, China) Sieve: Scalable In-Situ DRAM-Based Accelerator Designs for Massively Parallel k-mer FORMS: Fine-Grained Polarized ReRAM-Based In-Situ Computation  ... 
doi:10.1109/isca52012.2021.00004 fatcat:lg4ynhlbhbao3nojlr3wazky7u

Eliminating Dark Bandwidth: A Data-Centric View of Scalable, Efficient Performance, Post-Moore [chapter]

Jonathan C. Beard, Joshua Randall
2017 Lecture Notes in Computer Science  
Much computing research has focused on providing efficient compute, resulting in the compute cores found in today's CPU sockets.  ...  Most of computing research has focused on the computing technologies themselves versus how full systems make use of them (e.g., memory fabric, interconnect, software, and compute elements combined).  ...  is through in-/near-memory or in-storage rearrangement (there are better techniques for workloads with less compute intensity).  ... 
doi:10.1007/978-3-319-67630-2_9 fatcat:7tyhuw3k6jbgvlrau6yfizkram

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision [article]

Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park
2020 arXiv   pre-print
Our 128KB in/near memory computing architecture has been implemented using a 28nm CMOS process, and it can achieve 2.25GHz clock frequency at 1.0V with 5.2% of area overhead.  ...  This paper presents 6T SRAM cell-based bit-parallel in-memory computing (IMC) architecture to support various computations with reconfigurable bit-precision.  ...  Section 3 describes the proposed bit-parallel in/near-memory computing architecture for low-latency arithmetic operation with reconfigurable bit-precision.  ... 
arXiv:2008.03378v1 fatcat:gls4d42tingbhaxy6irgx3tjg4

Platform Independent Software Analysis for Near Memory Computing

Stefano Corda, Gagandeep Singh, Ahsan Jawed Awan, Roel Jordans, Henk Corporaal
2019 2019 22nd Euromicro Conference on Digital System Design (DSD)  
Near-memory Computing (NMC) promises improved performance for the applications that can exploit the features of emerging memory technologies such as 3D-stacked memory.  ...  Recent advancements in technology, however, have enabled us to bring the compute units in the proximity of data, which has lead to renewed interest in near-memory computing (NMC) architectures.  ...  Figure 2 depicts the reference computing platform that we consider in this work.  ... 
doi:10.1109/dsd.2019.00093 dblp:conf/dsd/CordaSAJC19 fatcat:uai2uxwxdnbqje2a55oxf66zna

TC-CIM: Empowering Tensor Comprehensions for Computation in Memory

Andi Drebes, Lorenzo Chelini, Oleksandr Zinenko, Albert Cohen, Henk Corporaal, Tobias Grosser, Kanishkan Vadivel, Nicolas Vasilache
2020 Zenodo  
hardware blocks implementing in-memory computations.  ...  Operations suitable for acceleration are identified using Loop Tactics, a declarative framework to describe computational patterns in a polyhedral representation.  ...  One of the main challenges in near-memory compilation is to decide which code portion should be offloaded to the accelerator.  ... 
doi:10.5281/zenodo.3736308 fatcat:k4yrzeo4jjdwvdrizc77poxblq

A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing [article]

Hongyang Jia, Yinqi Tang, Hossein Valavi, Jintao Zhang, Naveen Verma
2018 arXiv   pre-print
In-memory computing is a spatial architecture where processing elements correspond to dense bit cells, providing local storage and compute, typically employing analog operation.  ...  This paper describes a 590kb in-memory-computing accelerator integrated in a programmable processor architecture, by exploiting recent approaches to charge-domain in-memory computing.  ...  In addition to in/near-memory compute, the CIMU includes specialized interfaces for dataflow in a programmable architecture.  ... 
arXiv:1811.04047v1 fatcat:mh5r7ygzqzdgjln5l3thnt6adu

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

Gagandeep Singh, Lorenzo Chelini, Stefano Corda, Ahsan Javed Awan, Sander Stuijk, Roel Jordans, Henk Corporaal, Albert-Jan Boonstra
2018 2018 21st Euromicro Conference on Digital System Design (DSD)  
At the same time, the advancement in integration technologies have made the decade-old concept of coupling compute units close to the memory (called Near-Memory Computing) more viable.  ...  Using a case study, we present our methodology and also identify topics for future research to unlock the full potential of near-memory computing.  ...  CHALLENGES OF NEAR-MEMORY COMPUTING One of the biggest challenges in near-memory computing is the lack of interoperability with caches and virtual memory of the host processor due to unconventional programming  ... 
doi:10.1109/dsd.2018.00106 dblp:conf/dsd/SinghCCASJCB18 fatcat:26ucg3klobahff5mguj25lh44m

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Liang Chang, Chenglong Li, Zhaomin Zhang, Jianbiao Xiao, Qingsong Liu, Zhen Zhu, Weihang Li, Zixuan Zhu, Siqi Yang, Jun Zhou
2021 Science China Information Sciences  
However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture.  ...  Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM).  ...  Combined with the characteristics of non-volatile memory and timedomain computing, the ultra-low total power consumption of 1.02 µW was achieved in near memory architecture.  ... 
doi:10.1007/s11432-021-3234-0 fatcat:np7wtg24rzavbc5fsmammikn3i

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
2020 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs.  ...  The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations.  ...  TABLE III SUMMARY III OF DNN ACCELERATORS BASED ON IN/NEAR-MEMORY PROCESSING  ... 
doi:10.1109/jetcas.2020.3022920 fatcat:idqitgwnrnegbd4dhrly3xsxbi

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
Radical changes in computing are foreseen for the next decade.  ...  The US IEEE society wants to "reboot computing" and the HiPEAC Vision 2017 sees the time to "re-invent computing", both by challenging its basic assumptions.  ...  In near-memory, computing refers to the coupling of logic cores and e.g. hybrid memory cells; in-memory concepts refer on the coupling of NVM cell arrays and conventional CMOS that will work as memory  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

Experimental Demonstration of a Reconfigurable Coupled Oscillator Platform to Solve the Max-Cut Problem

Mohammad Khairul Bashar, Antik Mallick, Daniel S Truesdell, Benton H. Calhoun, Siddharth Joshi, Nikhil Shukla
2020 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits  
Leveraging the allto-all reconfigurable coupling architecture, we experimentally evaluate the computational properties of the oscillators using randomly generated graph instances of varying size and edge  ...  -/near-memory [20] - [22] .  ...  parametric oscillator-based coherent Ising machines (CIMs) [16] - [18] , and SRAM-based Ising machines that use CMOS annealing [19] , as well as the new CMOS annealing processors that use processing-in  ... 
doi:10.1109/jxcdc.2020.3025994 fatcat:6vzjzibcxvajlnuslrkbcnb35q

Many-Core Architecture for NTC: Energy Efficiency from the Ground Up [chapter]

Josep Torrellas
2016 Near Threshold Computing  
Among the techniques proposed are automatically managing the data in the cache hierarchy, processing in near-memory compute engines, and efficient fine-grained synchronization.  ...  However, to construct such a chip, we need to fundamentally rethink the whole compute stack from the ground up for energy efficiency.  ...  In addition, there are further concerns at both ends of the computing spectrum.  ... 
doi:10.1007/978-3-319-23389-5_2 fatcat:atnyaiyll5edlmnmtn7l5qgllu
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