Filters








15,267 Hits in 5.4 sec

Disk caching with an optical ring

Enrique V. Carrera, Ricardo Bianchini
2000 Applied Optics  
This latter evaluation shows that our optical ring improves performance for a traditional multiprocessor by roughly the same amount as it does for an optically interconnected multiprocessor.  ...  Our results demonstrate that our optical ring provides consistent performance improvements that derive mostly from faster page swap outs and victim caching.  ...  The authors would like to thank Luiz Monnerat, Cristiana Seidel, Rodrigo dos Santos, and Lauro Whately for comments that helped to improve the presentation of the paper.  ... 
doi:10.1364/ao.39.006663 pmid:18354681 fatcat:5k2pwihkpndvdalmzzavbafl2a

The impact of architectural trends on operating system performance

M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, A. Gupta
1995 ACM SIGOPS Operating Systems Review  
Because larger caches do not reduce coherence misses, the performance gap between uniprocessor and multiprocessor performance will increase unless operating system developers focus on kernel restructuring  ...  Using SimOS, a complete machine simulation environment, this paper explores the impact of the above architectural trends on operating system performance.  ...  We thank Sybase for providing us with their system and Ben Verghese for showing us how to use it. This study is part of the Stanford FLASH project, funded by ARPA Grant DABT63-94-C-0054.  ... 
doi:10.1145/224057.224078 fatcat:56e3x7q6bvevdgxgvpuznchfba

The impact of architectural trends on operating system performance

M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, A. Gupta
1995 Proceedings of the fifteenth ACM symposium on Operating systems principles - SOSP '95  
Because larger caches do not reduce coherence misses, the performance gap between uniprocessor and multiprocessor performance will increase unless operating system developers focus on kernel restructuring  ...  Using SimOS, a complete machine simulation environment, this paper explores the impact of the above architectural trends on operating system performance.  ...  We thank Sybase for providing us with their system and Ben Verghese for showing us how to use it. This study is part of the Stanford FLASH project, funded by ARPA Grant DABT63-94-C-0054.  ... 
doi:10.1145/224056.224078 dblp:conf/sosp/RosenblumBHWG95 fatcat:2comfp7ppvcrpage2i5ay4y7oy

The Non-blocking Programming Paradigm in Large Scale Scientific Computations [chapter]

Philippas Tsigas, Yi Zhang
2004 Lecture Notes in Computer Science  
Non-blocking implementation of shared data objects is a new alternative approach to the problem of designing scalable shared data objects for multiprocessor systems.  ...  In this paper, we try to provide an in depth understanding of the performance benefits of integrating non-blocking synchronisation in scientific computing applications.  ...  However when the data required by a processor is not in the cache, a cache miss, takes place and operations on memory still need to be performed.  ... 
doi:10.1007/978-3-540-24669-5_144 fatcat:q5yazlwvongxldthamm6ssastq

NWCache: Optimizing disk accesses via an optical network/write cache hybrid [chapter]

Enrique V. Carrera, Ricardo Bianchini
1999 Lecture Notes in Computer Science  
Our results demonstrate that the NWCache provides consistent performance improvements, coming mostly from faster page swap-outs, victim caching, and reduced contention.  ...  More specifically, we propose the use of an optical ring network for I/O operations that not only transfers swapped-out pages between the local memories and the disks, but also acts as a system-wide write  ...  Acknowledgements The authors would like to thank Luiz Monnerat, Cristiana Seidel, Rodrigo dos Santos, and Lauro Whately for comments that helped improve the presentation of the paper.  ... 
doi:10.1007/bfb0097971 fatcat:pniewjn52vgqdlidqn3su3zhkm

A Two Layered approach to perform Effective Page Replacement

Khusbu Rohilla
2013 IOSR Journal of Engineering  
The obtained results show that the presented work has improved the efficiency and reliability of the multiprocessor systems.  ...  Cache is small size memory available in system that holds both data and instruction. In case of shared cache, the management of cache is more critical.  ...  As the most required data items are in cache itself the system will improve the efficiency as well as will improve the hit ratio.  ... 
doi:10.9790/3021-031052125 fatcat:snwiq4teqzapni2gm2fk6cm47u

Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1

T. Suh, H.-H.S. Lee, D.M. Blough
2004 IEEE Micro  
Furthermore, we show that a snoophit buffer can improve the cache coherence performance.  ...  Like its homogeneous multiprocessor counterpart, the heterogeneous multiprocessor platform is in need of cache coherence support to enable data sharing in memory.  ... 
doi:10.1109/mm.2004.33 fatcat:ltfbpcs4dzd3noxh4443pv7tn4

Scalable and Flexible heterogeneous multi-core system

Rashmi, Dr. Dinesh
2012 International Journal of Advanced Computer Science and Applications  
Many researchers are aiming at improving the performance of these systems by providing flexible multi-core architecture.  ...  Use of high memory-level parallelism (MLP) reduces the memory wall. Micro architecture contains a set of small and fast cache processors which execute high locality code.  ...  Thread B can be migrated to multi-core processor A so that the shared data is located within a single shared cache, resulting in more rapidly access by both threads, leading to improved performance.  ... 
doi:10.14569/ijacsa.2012.031227 fatcat:m4vqub3x2fc7jlwm7dsb47ngzy

Shared Memory Multiprocessors [chapter]

2004 Parallel Computing on Heterogeneous Networks  
This involves looking for a cache line on every memory access issued by any processor in the system. Performing this lookup in the L1 cache could severely interfere with processor operation.  ...  There are three main sources of contention that can be found in a multiprocessor operating system: • Locks.  ... 
doi:10.1002/0471654167.ch3 fatcat:dvaj7kmetfgr7bkmdrmvzljwda

Optimizing IPC Performance for Shared-Memory Multiprocessors

Benjamin Gamsa, Orran Krieger, Michael Stumm
1994 1994 International Conference on Parallel Processing-Vol 1 (ICPP'94)  
The performance data we present demonstrates that the endto-end performance of our multiprocessor IPC facility is competitive with the fastest uniprocessor IPC times.  ...  In addition, such a multiprocessor IPC facility must preserve the locality and concurrency of the applications themselves so that the high performance of the IPC facility can be fully exploited.  ...  In a multiprocessor, accesses to shared data can result in cache misses or increased cache invalidation traffic which can add hundreds of cycles to the cost of an operation.  ... 
doi:10.1109/icpp.1994.144 dblp:conf/icpp/GamsaKS94 fatcat:c3wsymlkbja2xpmgdgckmwz35q

Study of Various Factors Affecting Performance of Multi-Core Processors

Nitin Chaturvedi, Gurunarayanan S
2013 International Journal of Distributed and Parallel systems  
As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip.  ...  This Paper presents analysis of various parameters affecting the performance of Multi-core Architectures like varying the number of cores, changes L2 cache size, further we have varied directory size from  ...  Multiple-CMP Because all of these systems use shared memory (to preserve operating system and application investment), a key challenge for M-CMP systems is implementing correct and high performance cache  ... 
doi:10.5121/ijdps.2013.4404 fatcat:ipcaejvdybaipejw5ehavdham4

Improving Web Server Performance Through Main Memory Compression

Vicenç Beltran, Jordi Torres, Eduard Ayguadé
2008 2008 14th IEEE International Conference on Parallel and Distributed Systems  
To solve this situation we propose the use of main memory compression techniques to increment the available memory and mitigate the disk bandwidth problem, allowing the web server to improve its use of  ...  resources provided by the system.  ...  Acknowledgments This work has been supported by the Spanish Ministry of Education and Science (projects TIN2007-60625), by the IBM SoW on Adaptive Systems, as part of the BSC-IBM collaboration agreement  ... 
doi:10.1109/icpads.2008.15 dblp:conf/icpads/BeltranTA08 fatcat:64snwbyedndljiqwrw22qpkud4

A performance evaluation of cache injection in bus-based shared memory multiprocessors

Aleksandar Milenkovic, Veljko Milutinovic
2002 Microprocessors and microsystems  
In these systems the high memory latency poses the major hurdle in achieving high performance. One way to cope with this problem is to use various techniques for tolerating high memory latency.  ...  Software-controlled cache prefetching and data forwarding are two widely used techniques for tolerating high memory latency in scalable cache-coherent shared memory multiprocessors.  ...  Efficiency of cache injection increases with the increase of the number of processors in the system, cache size, and memory latency.  ... 
doi:10.1016/s0141-9331(01)00146-6 fatcat:zajmkk23r5amvkv434oigd2m4y

A performance evaluation of the multiprocessor testbed ATTEMPT-0

Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano
1995 Parallel Computing  
By using the local memory, performance is improved 10 to 60% compared with the case of only the shared memory is used.  ...  The evaluation result demonstrates the efficiency of the cooperated system with the local memory, the synchronizer and the global shared memory.  ...  Jun-ichi Yamato now working at NEC corporation wrote the virtual memory support routines and some system software such as program loader.  ... 
doi:10.1016/0167-8191(94)00111-m fatcat:znq6pnqyffbodakuryywaqgjjy

Design and implementation of the NUMAchine multiprocessor

A. Grbic, M. Stumm, Z. Vranesic, Z. Zilic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
This paper describes the design and implementation of the NUMAchine multiprocessor.  ...  The key to the successful implementation of our 48-processor prototype is the use of off-the-shelf components and programmable logic devices.  ...  Performance Current Status Currently, a 4-station (16-processor) NUMAchine system is operational.  ... 
doi:10.1145/277044.277057 dblp:conf/dac/GrbicBCGGLLMSSVZ98 fatcat:zku2cnlt55cp5nshogbyxiqsly
« Previous Showing results 1 — 15 out of 15,267 results