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Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors

M. Durbhakula, V.S. Pai, S. Adve
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed.  ...  We compare the speed and accuracy of our new simulator, DirectRSIM, with three other simulators -RSIM (a detailed simulator for multiprocessors with ILP processors) and two representative simple-processor  ...  Acknowledgments We thank Jim Larus and Parthasarathy Ranganathan for valuable comments on earlier versions of this paper.  ... 
doi:10.1109/hpca.1999.744317 dblp:conf/hpca/DurbhakulaPA99 fatcat:6xuxsfuqy5azvizlwfhqvckoqy

FLASH vs. (Simulated) FLASH

Jeff Gibson, Robert Kunz, David Ofelt, Mark Horowitz, John Hennessy, Mark Heinrich
2000 Proceedings of the ninth international conference on Architectural support for programming languages and operating systems - ASPLOS-IX  
One significant problem with simulation is that it rarely models the system exactly, and quantifying the resulting simulator error can be difficult.  ...  Simulation is the primary method for evaluating computer systems during all phases of the design process.  ...  ACKNOWLEDGMENTS We would like to thank Robert Bosch for his help in configuring the MXS simulator. Robert and Kinshuk Govil also provided valuable assistance in debugging simulator problems.  ... 
doi:10.1145/378993.379000 fatcat:phyvhntymfctjdkbo4cfcqz2om

Understanding PARSEC performance on contemporary CMPs

Major Bhadauria, Vincent M. Weaver, Sally A. McKee
2009 2009 IEEE International Symposium on Workload Characterization (IISWC)  
To reduce power and improve performance, we recommend increasing the number of arithmetic units per core, increasing support for TLP, and reducing support for ILP.  ...  threads, number of memory channels, and processor frequencies.  ...  Without it, our insights on the Sun SPARC platform would not have been possible. We also thank Chris Fensch from the University of Cambridge for his patches to enable execution on the SPARC platform.  ... 
doi:10.1109/iiswc.2009.5306793 dblp:conf/iiswc/BhadauriaWM09 fatcat:qx5lefg44ncnxc7ur34f3yvn4q

The Wisconsin Wind Tunnel project

Mark D. Hill, James R. Larus, David A. Wood
1994 SIGARCH Computer Architecture News  
This document lists contributors to the Wisconsin Wind Tunnel Project, gives a brief description of the project, and presents references and abstracts to its principal papers, including how to obtain them  ...  Our new out-of-order processor simulator, FastSim, uses two innovations to speed up simulation 8-15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy.  ...  In this paper, we use the Wisconsin Wind Tunnel, a parallel simulator for cache-coherent shared-memory machines, to study the trade-offs of accuracy versus performance for six different network simulation  ... 
doi:10.1145/192537.192543 fatcat:rvtgkgeonnba3cdbociaiglrdq

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 SIGARCH Computer Architecture News  
conventional multiprocessors with similar execution resources.  ...  We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding  ...  Acknowledgments We would like to thank John O'Donnell from Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/225830.224449 fatcat:gtheubj4tbcqxokcmbrfoihxym

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95  
conventional multiprocessors with similar execution resources.  ...  We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding  ...  Acknowledgments We would like to thank John O'Donnell from Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/223982.224449 dblp:conf/isca/TullsenEL95 fatcat:rj3illxasbalhkiz4ygcsjsvdi

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
multiprocessors with similar execution resources. while simultaneous multitbreading has excellent potential to increase processor utilization, it can add substantial complexity to the design.  ...  WC also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform comiponding conventional  ...  Acknowledgments We would like to thank JohnO'Donnell from EquatorTechnologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/285930.286011 dblp:conf/isca/TullsenEL98a fatcat:wzwmqqcnj5bz3faupjps7d6tay

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, David Brooks
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.  ...  Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization.  ...  Acknowledgements We thank the anonymous reviewers for their feedback on numerous manuscripts. Moreover, we would like to thank Glenn Holloway for his invaluable contributions to the HELIX project.  ... 
doi:10.1109/isca.2014.6853215 dblp:conf/isca/CampanoniBKJWB14 fatcat:uv7k7p2v4bf2pklh4fgnmkuvma

HELIX-RC

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, David Brooks
2014 SIGARCH Computer Architecture News  
Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.  ...  Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization.  ...  Acknowledgements We thank the anonymous reviewers for their feedback on numerous manuscripts. Moreover, we would like to thank Glenn Holloway for his invaluable contributions to the HELIX project.  ... 
doi:10.1145/2678373.2665705 fatcat:g5va7ht7wndb7lec5ar3udp5g4

A perspective on the future of massively parallel computing

Predrag T. Tosic
2004 Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04  
We conclude with some brief remarks on the role that the paradigms, concepts, and design ideas originating from the connectionist models have already had in the existing parallel design, and what further  ...  Models, architectures and languages for parallel computation have been of utmost research interest in computer science and engineering for several decades.  ...  Acknowledgments The author is greatly indebted to Gul Agha, Tom Anastasio, Alfred Hubler and Sylvian Ray, all at University of Illinois.  ... 
doi:10.1145/977091.977160 dblp:conf/cf/Tosic04 fatcat:5jhbmelpzndxno4447xbzs6sk4

A Survey of Computer Architecture Simulation Techniques and Tools

Ayaz Akram, Lina Sawalha
2019 IEEE Access  
Comparing computer architecture simulators with each other and validating their accuracy have been demanding tasks for architects.  ...  With wider research directions and the increased number of simulators that have been developed, it becomes harder to choose a particular simulator to use.  ...  ACKNOWLEDGEMENT The authors would like to thank the anonymous reviewers for their valuable feedback and comments.  ... 
doi:10.1109/access.2019.2917698 fatcat:zbf5dapusrewbiti6pmgg6le74

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

Kunle Olukotun, Lance Hammond, James Laudon
2007 Synthesis Lectures on Computer Architecture  
The gains in OLTP were also mostly from the faster clock cycle, since the relative improvement in memory latencies compared to processor speed was smaller.  ...  required, in addition to the sharing possible with a conventional multiprocessor.  ...  computation for graphics and simulation.  ... 
doi:10.2200/s00093ed1v01y200707cac003 fatcat:qyjilavdhfcmlnc46l5sxg7ssq

Managing dynamic concurrent tasks in embedded real-time multimedia systems

Peng Yang, Paul Marchal, Chun Wong, Stefaan Himpe, Francky Catthoor, Patrick David, Johan Vounckx, Rudy Lauwereins
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way.  ...  A two-phase scheduling method is used for that purpose.  ...  The promising results that can be obtained with such a methodology will be illustrated with an MPEG21 based demonstrator mapped on a multi-processor simulation platform with a hierarchical share memory  ... 
doi:10.1145/581199.581226 fatcat:woumou2odjbmnkloc3cdubfgry

Managing dynamic concurrent tasks in embedded real-time multimedia systems

Peng Yang, Paul Marchal, Chun Wong, Stefaan Himpe, Francky Catthoor, Patrick David, Johan Vounckx, Rudy Lauwereins
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way.  ...  A two-phase scheduling method is used for that purpose.  ...  The promising results that can be obtained with such a methodology will be illustrated with an MPEG21 based demonstrator mapped on a multi-processor simulation platform with a hierarchical share memory  ... 
doi:10.1145/581225.581226 fatcat:r5dcsy7udjfttmwg4itsjaqifq

Leveraging the Openness and Modularity of RISC-V in Space

Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone
2019 Journal of Aerospace Information Systems  
Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions.  ...  , 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence.  ...  Acknowledgments This work was supported by the European Space Agency under the NPI Program, Cobham Gaisler AB, and Delft University of Technology.  ... 
doi:10.2514/1.i010735 fatcat:b4ckmbr2uvhvzi57ltesqyiokm
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