2,062 Hits in 6.8 sec

PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis

Jeff Hao, Valeria Bertacco
2009 2009 IEEE International High Level Design Validation and Test Workshop  
In this paper, we propose PowerRanger, a technique based on Boolean satisfiability to produce tight upper and lower bounds on both maximum and minimum power dissipation.  ...  By monitoring the power dissipation of a core, an attacker can extract secret keys used for encryption.  ...  To improve the scalability of our approach, we use a partitioning algorithm to divide the circuit into smaller blocks.  ... 
doi:10.1109/hldvt.2009.5340174 dblp:conf/hldvt/HaoB09 fatcat:yrgl7ewf3nc6tcua4ezedp7zha

SAT-based Circuit Local Improvement [article]

Alexander S. Kulikov, Danila Pechenev, Nikita Slezkin
2022 arXiv   pre-print
Through this approach, we prove new upper bounds on the circuit size of various symmetric functions.  ...  by reducing to SAT.  ...  The improved upper bounds are obtained in a semiautomatic fashion: 1. first, we automatically improve a given small circuit with a fixed number of inputs using SAT-solvers; 2. then, we generalize it to  ... 
arXiv:2102.12579v3 fatcat:kvmebueahrbsblcw67pwtxcdvm

On speeding up factoring with quantum SAT solvers [article]

Michele Mosca, João Marcos Vensi Basso, Sebastian R. Verschoor
2019 arXiv   pre-print
We present a SAT circuit that can be given to quantum SAT solvers such as annealers in order to perform this step of factoring.  ...  In this paper the use of SAT solvers is restricted to a smaller task related to factoring: finding smooth numbers, which is an essential step of the Number Field Sieve.  ...  The ECM circuit can be designed to have size upper-bounded by L N [1/6, 2β/3 + o(1)] and probability of success 1 − o(1). Proof.  ... 
arXiv:1910.09592v1 fatcat:midal5jgsbcqpmksry56epgyaa

New upper bounds on the Boolean circuit complexity of symmetric functions

E. Demenkov, A. Kojevnikov, A. Kulikov, G. Yaroslavtsev
2010 Information Processing Letters  
In this note, we present improved upper bounds on the circuit complexity of symmetric Boolean functions.  ...  In particular, we describe circuits of size 4.5n + o(n) for any symmetric function of n variables, as well as circuits of size 3n for MOD n 3 function.  ...  Modern SAT-solvers were not able to improve upper bounds for other MOD k functions: for k ≥ 5, the corresponding CNF formulas are too large. x y z u 0 u 1 ⊕ g 1 ¬ ∨ g 2 ⊕ g 3 ⊕ g 4 ⊕ g 5 ∧ g 6 ⊕ g 7 ¬  ... 
doi:10.1016/j.ipl.2010.01.007 fatcat:oaghvbax65bwnkxkc7kuth45ia

On speeding up factoring with quantum SAT solvers

Michele Mosca, Joao Marcos Vensi Basso, Sebastian R. Verschoor
2020 Scientific Reports  
We present a SAT circuit that can be given to quantum SAT solvers such as annealers in order to perform this step of factoring.  ...  In this paper the use of SAT solvers is restricted to a smaller task related to factoring: finding smooth numbers, which is an essential step of the Number Field Sieve.  ...  Theorem 3 3 The ECM circuit can be designed to have size upper-bounded by L N [1/6, √ 2β/3 + o(1)] and probability of success 1 − o(1).  ... 
doi:10.1038/s41598-020-71654-y pmid:32929125 fatcat:ghggznrlqjeg7jx2kwkbrh3kdi

Using interval constraint propagation for pseudo-Boolean constraint solving

Karsten Scheibler, Bernd Becker
2014 2014 Formal Methods in Computer-Aided Design (FMCAD)  
This work is motivated by (1) a practical application which automatically generates test patterns for integrated circuits and (2) the observation that off-the-shelf state-of-the-art pseudo-Boolean solvers  ...  Derived from the SMT solver iSAT3 we present the solver iSAT3p that on the one hand allows the efficient handling of huge pseudo-Boolean constraints with several thousand summands and large integer coefficients  ...  The fact that iSAT3p has a SAT solver in its core enables us to use all the merits of a BDD-based SAT translation.  ... 
doi:10.1109/fmcad.2014.6987614 dblp:conf/fmcad/ScheiblerB14 fatcat:5clihi34rfgxxnjsqa4zdoqtcy

Faster Sorting Networks for 17, 19 and 20 Inputs [article]

Thorsten Ehlers, Mike Müller
2014 arXiv   pre-print
Therefore, we improve upon the known upper bounds for minimal depth sorting networks on 17, 19, and 20 channels.  ...  The networks were obtained using a combination of hand-crafted first layers and a SAT encoding of sorting networks.  ...  logic and used a SAT solver to show that the resulting formulae are unsatisfiable.  ... 
arXiv:1410.2736v1 fatcat:2ikdabpafrdxleuzi4kajvuky4

Optimal trace compaction with property preservation

Yibin Chen, Sean Safarpour, Andreas Veneris
2009 2009 52nd IEEE International Midwest Symposium on Circuits and Systems  
improvement.  ...  The approach builds a SAT instance from the Iterative Logic Array representation of the circuit and performs a binary search to find the minimum trace length.  ...  Our trace compaction algorithm first obtains an upper bound for the minimal trace length using SAT and then employs a binary search using incremental SAT to find an optimal trace.  ... 
doi:10.1109/mwscas.2009.5235932 fatcat:qw3s5ohqjrd3xball5c4q4fu54

Using SAT-based techniques in power estimation

Assim Sagahyroon, Fadi A. Aloul
2007 Microelectronics Journal  
Both problems were successfully formulated as SAT problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution.  ...  SAT is increasingly being used as the underlying model for a number of applications in EDA.  ...  Results indicate that by using these solvers we can improve on randombased approaches. Furthermore, generic ILP solvers tend to outperform SAT-based 0-1 ILP solvers on the proposed problems.  ... 
doi:10.1016/j.mejo.2007.05.001 fatcat:v3qzs5yr5bf6jlpdyynokdzkcu

Factoring semi-primes with (quantum) SAT-solvers [article]

Michele Mosca, Sebastian R. Verschoor
2019 arXiv   pre-print
While reducing factoring to SAT has proved to be useful for studying SAT solvers, attempting to factor large integers via such a reduction has not been found to be successful.  ...  Since integer factorization is in NP, one can reduce this problem to any NP-hard problem, such as Boolean Satisfiability (SAT).  ...  Acknowledgment We would like to thank Vijay Ganesh and Curtis Bright for the many lessons about modern SAT solving and insightful discussions regarding this project.  ... 
arXiv:1902.01448v2 fatcat:ytdqkeiqk5aybaljsryp75o3by

The Circuit-Input Game, Natural Proofs, and Testing Circuits With Data

Brynmor Chapman, Ryan Williams
2015 Proceedings of the 2015 Conference on Innovations in Theoretical Computer Science - ITCS '15  
Slightly more precisely, we prove NP ⊂ P/poly if and only if there are natural properties that (a) accept the SAT function and (b) are useful against polynomial-size circuits that never err when they report  ...  We give two new applications of these classical results to circuit complexity: Natural properties useful against self-checking circuits are equivalent to circuit lower bounds.  ...  In particular, one reviewer improved an earlier version of Theorem 2.3.  ... 
doi:10.1145/2688073.2688115 dblp:conf/innovations/ChapmanW15 fatcat:dxgjg4xysnebvjhabo7uss6caa

Successful SAT Encoding Techniques

Magnus Björk
2009 Journal on Satisfiability, Boolean Modeling and Computation  
There is consensus that encoding techniques usually have a dramatic impact on the efficiency of the SAT solver, that it often takes much work to find a good encoding, and that the size of an encoding is  ...  Topics where the interviewees disagree include the feasibility of including arithmetics in SAT problems and whether to formulate problems as clauses or circuits.  ...  MiniSat, PicoSat, and BarceLogic are all examples of CDCL SAT solvers. Baumgartner et al use a hybrid circuit SAT solver, that operates directly on circuits 1.  ... 
doi:10.3233/sat190085 fatcat:eyglyumxkrexdf5p2dpriolz2a

SAT-based fault coverage evaluation in the presence of unknown values

M A Kochte, H-J Wunderlich
2011 2011 Design, Automation & Test in Europe  
The algorithm is compared to related work and evaluated on benchmark and industrial circuits.  ...  Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality.  ...  This information is used to assess the precision of the proposed algorithm (c.f. section V-C). Due to the small sample size of 128 patterns only, the computed coverage is an optimistic upper bound.  ... 
doi:10.1109/date.2011.5763209 dblp:conf/date/KochteW11 fatcat:3rzuieftm5dhfjb7u7rbvrglxy


Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010 Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems - DYADEM-FTS '10  
Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality.  ...  Automated support is required to analyze the fault tolerance of circuits. In this paper, ROBUCHECK is presented -a design tool to analyze the fault tolerance of digital circuits.  ...  The SECengine and the ATPG-engine use a solver for Boolean Satisfi- ability (SAT) as a back-end [5] , [6] .  ... 
doi:10.1145/1772630.1772641 fatcat:ho4hr6bv2zex5n72juau4a3ave

The Complexity of Satisfiability of Small Depth Circuits [chapter]

Chris Calabro, Russell Impagliazzo, Ramamohan Paturi
2009 Lecture Notes in Computer Science  
We show an improved randomized algorithm for the satisfiability problem for circuits of constant depth d and a linear number of gates cn: for each d and c, the running time is 2 (1−δ)n where the improvement  ...  The algorithm can be adjusted for use with Grover's algorithm to achieve a run time of 2 1−δ 2 n on a quantum computer.  ...  Acknowledgments: We would like to thank Mike Saks for useful discussions.  ... 
doi:10.1007/978-3-642-11269-0_6 fatcat:wip2jerrsndgtjmbz2nzv26r7e
« Previous Showing results 1 — 15 out of 2,062 results