Filters








4,924 Hits in 6.3 sec

Improving and Estimating the Precision of Bounds on the Worst-Case Latency of Task Chains

Alain Girault, Christophe Prevot, Sophie Quinton, Rafik Henia, Nicolas Sordon
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Compared to the state of the art, our analysis provides upper bounds on the WCEL in the more general case of asynchronous task chains, and also provides lower bounds on the WCEL both for synchronous and  ...  Computing the worst-case end-to-end latency (WCEL) of each chain is complex because of the intricate relationship between the task priorities.  ...  Based on the computed lower bounds, we can estimate the precision of the computed upper bound on the latency of each task chain. The paper is organized as follows.  ... 
doi:10.1109/tcad.2018.2861016 fatcat:4jd64mtdkjeo7ifrgq2uyaqedm

Response-Time Analysis for Task Chains in Communicating Threads

Johannes Schlatow, Rolf Ernst
2016 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)  
We evaluated the extended busy-window analysis in a compositional performance analysis using synthetic test cases and a realistic automotive use case showing far tighter response-time bounds than current  ...  As these task chains represent a functionally-dependent sequence of operations, in real-time systems, there is usually a requirement for their end-to-end latency.  ...  ACKNOWLEDGEMENTS This work was supported by the DFG Research Unit Controlling Concurrent Change (CCC), funding number FOR 1800. We thank the members of CCC for their support.  ... 
doi:10.1109/rtas.2016.7461359 dblp:conf/rtas/SchlatowE16 fatcat:xyblvsdnlbhpvmghjnmocf2ndm

Methods, tools and standards for the analysis, evaluation and design of modern automotive architectures

E. Frank, R. Wilhelm, R. Ernst, A. Sangiovanni-Vincentelli, M. Di Natale
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
In this paper, we review methods and tools for the evaluation of the function performance and its timing correctness by simulation or by worst case static analysis.  ...  Hence, the need for methods and tools capable of predicting the system-level timing behaviour (latencies and jitter), resulting from the HW platform selection, the synchronization between tasks and messages  ...  In absence of faults, and assuming that the worst case execution time of a task can be safely estimated, these standards allow predicting the worst-case timing behavior of computations and communications  ... 
doi:10.1145/1403375.1403536 fatcat:pexnjaqhzrc6xaftdytuzu2eue

End-to-end latency and temporal consistency analysis in networked real-time systems

Michaël Lauer, Frédéric Boniol, Claire Pagetti, Jérôme Ermont
2014 International Journal of Critical Computer-Based Systems  
worst case response time of a task) or on the networks (e.g., worst case traversal time of a message).  ...  Such a property applies to functional chains which describe the behaviour of sequences of tasks.  ...  Worst case temporal consistency An upper bound on the worst case consistency is given by the maximum difference between the worst case and best case latency of the functional chains.  ... 
doi:10.1504/ijccbs.2014.064667 fatcat:uddd2iyoqjemrino4mrsijccfy

Integrated analysis of communicating tasks in MPSoCs

Simon Schliecker, Matthias Ivers, Rolf Ernst
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside a component,  ...  Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures -which could not be addressed on a single level alone.  ...  An important property of real time systems is the path or chain latency that is given by the worst case latency of any event from an input via a specific chain of tasks to an output.  ... 
doi:10.1145/1176254.1176325 dblp:conf/codes/SchlieckerIE06 fatcat:jqpspxpumfarbd7xdgo3ixrh3i

Estimating Latencies of Task Sequences in Multi-Core Automotive ECUs [article]

Max J. Friese and Thorsten Ehlers and Dirk Nowotka
2018 arXiv   pre-print
The delay between stimulus and reaction thus depends on the interaction of these tasks and is subject to timing constraints.  ...  It is the first formal analysis approach making use of load assumptions in order to exclude infeasible data propagation paths without the knowledge of worst-case execution times or worst-case response  ...  This is done by analyzing the part of the systemlevel cause effect chain which starts at the receiving network task of the ECU and ends at the corresponding network task to propagate the stimulus or a  ... 
arXiv:1804.07647v1 fatcat:pvcmbbmnoncsff4cjbaotsgife

PSO based optimization of worst-case execution time for ASIP application

Mood Venkanna, Rameshwar Rao, P Chandra Sekhar
2018 International Journal of Engineering & Technology  
The estimation of upper bound limits corresponding to the execution times is often termed as the Worst-Case Execution Times (WCETs).  ...  Hard Real-Time Systems' embedded controllers are with expectation of complete the tasks within a certain time bounds reliably including task scheduling.  ...  To accomplish this task the worst-case path latency is by inserting a CI and to generate an entirely new different path.  ... 
doi:10.14419/ijet.v7i2.33.14162 fatcat:2whdhmpp2vczrm2kxf6agerd3a

Latency analysis for data chains of real-time periodic tasks

Tomasz Kloda, Antoine Bertout, Yves Sorel
2018 2018 IEEE 23rd International Conference on Emerging Technologies and Factory Automation (ETFA)  
We propose a method for the worst-case latency calculation of periodic tasks' data chains executed by a partitioned fixed-priority preemptive scheduler upon a multiprocessor platform.  ...  In this paper, we focus on the latency computation, considered as the time elapsed from getting the data from an input and processing it to an output of a data chain.  ...  Acknowledgements This research has been partially funded by the French FUI Waruna project.  ... 
doi:10.1109/etfa.2018.8502498 dblp:conf/etfa/KlodaBS18 fatcat:dxm2pnaxffdn7bndsnfjjxl2mi

Challenges and Solutions in the Development of Automotive Systems

Alberto Sangiovanni-Vicentelli, Marco Di Natale
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
the best-case and the worst-case delays.  ...  Careful timing analysis is also required to avoid timing faults when scheduling tasks and messages either by priority or in a time-triggered scheduling environment, provided an estimate of the worst-case  ... 
doi:10.1109/tcad.2009.2024982 fatcat:f66lzih3i5dvxfkkzoao5uokzy

Estimating End-to-End Latencies in Automotive Cyber-physical Systems

Max J. Friese, Dirk Nowotka
2020 Electronic Proceedings in Theoretical Computer Science  
However, most work is limited to either network latencies or software latencies which results in an analysis gap at the transition between different layers of the communication stack.  ...  Consequently, to ensure safety and comfort, a performance analysis is an inherent part of the engineering process. Conducting such an analysis manually is expensive, slow, and error prone.  ...  For the software part, the possible core execution times of the involved tasks and the dataflow through the tasks is analyzed to find the path which yields the worst-case latency.  ... 
doi:10.4204/eptcs.316.6 fatcat:cqlbmnqu6jhifelt2av2kbk6em

Data-Age Analysis and Optimisation for Cause-Effect Chains in Automotive Control Systems

Johannes Schlatow, Mischa Mostl, Sebastian Tobuschat, Tasuku Ishigooka, Rolf Ernst
2018 2018 IEEE 13th International Symposium on Industrial Embedded Systems (SIES)  
When implementing and integrating these systems, these latency requirements must be guaranteed e.g. by applying a worst-case analysis that takes all indeterminism and limited predictability of the timing  ...  We particularly focus on data age as one representative of the two most common latency semantics.  ...  ACKNOWLEDGEMENT This work was partially funded within the DFG Research Unit CCC, funding number FOR 1800, and partially by Hitachi Ltd. We further thank Thorsten Koch for providing ZIMPL [15] .  ... 
doi:10.1109/sies.2018.8442077 dblp:conf/sies/SchlatowMTIE18 fatcat:4d7tnph755g4ld5cajlp6l54qa

Compositional Performance Analysis [chapter]

Robin Hofman, Leonie Ahrendts, Rolf Ernst
2017 Zenodo  
In this chapter we review the foundations Compositional Performance Analysis (CPA) and explain many extensions which support its application in design practice.  ...  Acknowledgements The project leading to this overview has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 644080 as well as from the German  ...  Research Foundation (DFG) under the contract number TWCA ER168/30-1.  ... 
doi:10.5281/zenodo.997937 fatcat:axgyxbuubnakpmclvzpdcu6lp4

High-level real-time programming in Java

David F. Bacon, Martin T. Vechev, Perry Cheng, David Grove, Michael Hind, V. T. Rajan, Eran Yahav, Matthias Hauswirth, Christoph M. Kirsch, Daniel Spoonhower
2005 Proceedings of the 5th ACM international conference on Embedded software - EMSOFT '05  
Our goals include construction of a provably correct real-time garbage collector capable of providing worst case latencies of 100 µs, capable of scaling from sensor nodes up to large multiprocessors; specialized  ...  to timing behavior; online analysis and visualization that aids in the understanding of complex behaviors; and a principled probabilistic analysis methodology for bounding the behavior of the resulting  ...  Acknowledgments Much of this work was done in the IBM J9 virtual machine, and would not have been possible without the use of that infrastructure or the assistance of the J9 team, in particular Pat Dubroy  ... 
doi:10.1145/1086228.1086242 dblp:conf/emsoft/BaconCGHRYHKSV05 fatcat:z37bw5vr7jcwfn5vsycbcafn7y

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clement David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou (+8 others)
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017  
In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach.  ...  The ARGO H2020 project 1 provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the  ...  WCET-analysis for heterogeneous multi-and many-core architectures to provide strict upper bounds of the system's worst-case execution time.  ... 
doi:10.23919/date.2017.7927000 dblp:conf/date/DerrienPABBDDDF17 fatcat:7d3ac4uwwrb6llwboieuajjuqu

Mathematical formalisms for performance evaluation of networks-on-chip

Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu
2013 ACM Computing Surveys  
The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis.  ...  This article reviews four popular mathematical formalisms-queueing theory, network calculus, schedulability analysis, and dataflow analysis-and how they have been applied to the analysis of on-chip communication  ...  ACKNOWLEDGMENT The authors would like to thank the reviewers for their valuable comments and suggestions.  ... 
doi:10.1145/2480741.2480755 fatcat:wwlsqn7arng7hcgu4lxwbpdf3u
« Previous Showing results 1 — 15 out of 4,924 results