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UltraSPARC-III: designing third-generation 64-bit performance

T. Horel, G. Lauterbach
<span title="">1999</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
The UltraSPARC-III is the third generation of Sun Microsystems' most powerful microprocessors, which are at the heart of Sun's computer systems.  ...  The UltraSPARC-III design target is a 600-MHz, 70-watt, 19-mm die to be built in 0.25-micron CMOS with six metal layers for signals, clocks, and power.  ...  arithmetic, logical, and shift instructions; read, and check dependency of, first cycle of data cache access floating-point register file C Access second cycle of data cache, and forward load data  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.768506">doi:10.1109/40.768506</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/p7kctxbznbdcfhfu35zp67ngxy">fatcat:p7kctxbznbdcfhfu35zp67ngxy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829231159/http://gec.di.uminho.pt/discip/minf/ac0203/ICCA03/UltraSPARC.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cd/68/cd6875c9adcbe94b420bb0774b1909affea52153.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/40.768506"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications [article]

Mehdi Alipour, Mostafa E. Salehi, Hesamodin shojaei baghini
<span title="2012-05-09">2012</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Experimental results show that although having bigger cache and register file is one of the performance improvement approaches in embedded processors, however, by increasing the size of these parameters  ...  Since the processor performance is severely related to the average memory access delay and also the number of processor registers affects the performance, cache and register file are two major parts in  ...  To improve the performance of a embedded processor, a large register file must be implemented. However, larger register files occupy more area and make a worse critical path [18] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1205.1871v1">arXiv:1205.1871v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wbocwq4na5fvpc6uichxrgkzj4">fatcat:wbocwq4na5fvpc6uichxrgkzj4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200826041624/https://arxiv.org/ftp/arxiv/papers/1205/1205.1871.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/21/61/21619ecab0ffa51014694d62a56ce865633576db.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1205.1871v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Power reduction through work reuse

Emil Talpes, Diana Marculescu
<span title="">2001</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qcoemsk4lfgznflartfnzb5rhy" style="color: black;">Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED &#39;01</a> </i> &nbsp;
Traditionally, these concerns are addressed through semiconductor technology improvements such as voltage reduction and technology scaling.  ...  The rapid increase in complexity and speed that comes with each new CPU generation causes greater problems with power consumption and heat dissipation.  ...  ACKNOWLEDGEMENTS The authors would like to thank John Shen of Carnegie Mellon University/Intel Corp. for many stimulating discussions, as well as for offering many insights into the TurboScalar microarchitecture  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/383082.383180">doi:10.1145/383082.383180</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/islped/TalpesM01.html">dblp:conf/islped/TalpesM01</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/axtj4qermbbmzh3bzhkvcgrvum">fatcat:axtj4qermbbmzh3bzhkvcgrvum</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706122102/http://www.cecs.uci.edu/~papers/compendium94-03/papers/2001/islped01/pdffiles/p340.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d8/1d/d81da3ad5388fc4779a5c35564cd195130fc10b9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/383082.383180"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

The design of a microsupercomputer

T.N. Mudge, R.B. Brown, W.P. Birmingham, J.A. Dykstra, A.I. Kayssi, R.J. Lomax, O.A. Olukotun, K.A. Sakallah, R.A. Milano
<span title="">1991</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dsrvu6bllzai7oj3hktnc5yf4q" style="color: black;">Computer</a> </i> &nbsp;
These are critical integration levels because they allow the number of chip crossings on the critical timing path of an instruction to be limited to just two (accessing an off-chip cache).  ...  Our circuit simulations of the processor, verified by fabrication and testing of the register file and arithmetic logic unit,4 indicate that it can be clocked at 250 MHz. 57  ...  We gratefully acknowledge the assistance of Seattle Silicon Corporation and Mentor Graphics Corporation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/2.67194">doi:10.1109/2.67194</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sp2rjxqeijcy3gzpwyqwjnzooi">fatcat:sp2rjxqeijcy3gzpwyqwjnzooi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170813154931/http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/1991.01.The%20Design%20Of%20A%20Micro-Supercomputer_Computer.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/10/1e/101e6bcc1fa9f8aac349b229a5f290d27d8c8d06.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/2.67194"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Seongmoo Heo, Kenneth Barr, Mark Hampton, Krste Asanović
<span title="2002-05-01">2002</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/35q3ync5nbhnjfpylznlz57lyi" style="color: black;">SIGARCH Computer Architecture News</a> </i> &nbsp;
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings.  ...  Using leakage-biased bitlines to deactivate SRAM read paths within I-cache memories saves over 24% of leakage energy and 22% of total I-cache energy when using a 70 nm process.  ...  This work was funded by DARPA PAC/C award F30602-00-2-0562, NSF CAREER award CCR-0093354, and a donation from Infineon Technologies.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/545214.545231">doi:10.1145/545214.545231</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/p7aivcpjkbelnmzn3del4rfnsy">fatcat:p7aivcpjkbelnmzn3del4rfnsy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170922022100/http://scale.eecs.berkeley.edu/papers/leakage-isca2002.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/77/7a/777a1e26173dfa0c9128174cf370831da5d412ed.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/545214.545231"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

A spatial path scheduling algorithm for EDGE architectures

Katherine E. Coons, Xia Chen, Doug Burger, Kathryn S. McKinley, Sundeep K. Kushwaha
<span title="2006-10-16">2006</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/xu5bk2lj5rbdxlx6222nw7tsxi" style="color: black;">SIGPLAN notices</a> </i> &nbsp;
We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of  ...  We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation.  ...  We would also like to thank Bert Maher and Behnam Robatmili for the use of their condor cycles.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1168918.1168875">doi:10.1145/1168918.1168875</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/26dbkbknnbcxboxlbwigx4fdui">fatcat:26dbkbknnbcxboxlbwigx4fdui</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20070117210117/http://www.cs.utexas.edu:80/users/cart/trips/publications/asplos06.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7b/ab/7babdefa08df7b88c5afa5c8a9da9231018cd7a9.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1168918.1168875"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Register Pointer Architecture for Efficient Embedded Processors

JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">2007 Design, Automation &amp; Test in Europe Conference &amp; Exhibition</a> </i> &nbsp;
Conventional register file architectures cannot optimally exploit temporal locality in data references due to their limited capacity and static encoding of register addresses in instructions.  ...  Indirection allows a larger register file to be used without increasing the length of instruction words.  ...  file consumes 5% of the total processor power and register file with 64 entries dissipate 47% more power than register file with 16 entries.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2007.364659">doi:10.1109/date.2007.364659</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/ParkPBBKD07.html">dblp:conf/date/ParkPBBKD07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4gmk2jdkh5artbqhvuzgbbz7m4">fatcat:4gmk2jdkh5artbqhvuzgbbz7m4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20071023232515/http://www.date-conference.com/conference/proceedings/PAPERS/2007/DATE07/PDFFILES/04.5_4.PDF" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/dc/53/dc530033d51f1ca9822a8e48b78aea4a0be9f687.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2007.364659"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Performance-Optimum Superscalar Architecture for Embedded Applications [article]

Mehdi Alipour, Mostafa E. Salehi
<span title="2012-04-12">2012</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Although increasing cache and register file size leads to performance improvements in high performance embedded processors, the increased area, power consumption and memory delay are the overheads of these  ...  This paper explores the effect of cache, register file and superscalar parameters on the processor performance to specify the optimum size of these parameters for embedded applications.  ...  However, large register file occupies large area and increases the critical path [29, 30] therefore, obtaining the optimum size of the register file is the second purpose of this paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1204.2809v1">arXiv:1204.2809v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/m55veykve5ei7flfnhemxejnwm">fatcat:m55veykve5ei7flfnhemxejnwm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200929061720/https://arxiv.org/ftp/arxiv/papers/1204/1204.2809.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d7/c0/d7c01803a82ebe0c3e5dc1a0d142c34f93490590.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1204.2809v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Application adaptive energy efficient clustered architectures

Diana Marculescu
<span title="">2004</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qcoemsk4lfgznflartfnzb5rhy" style="color: black;">Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED &#39;04</a> </i> &nbsp;
or non-critical and adapting to changes in the criticality of such code portions.  ...  This paper proposes a clustered architecture that enables applicationadaptive energy efficiency through the use of dynamic voltage scaling for application code that is rendered non-critical for the overall  ...  Out-of-order execution was accomplished through the use of issue queues and a register file instead of the default register update unit/load store queue (RUU/LSQ) combination.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1013235.1013318">doi:10.1145/1013235.1013318</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/islped/Marculescu04.html">dblp:conf/islped/Marculescu04</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7lsbhtkp5bhjpko4pnkdbyg22i">fatcat:7lsbhtkp5bhjpko4pnkdbyg22i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808192532/https://users.ece.cmu.edu/~dianam/conferences/islped04-1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f9/f6/f9f62acffe3dfb6f2925d6d25b103e7de65eb6d8.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1013235.1013318"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

CGaAs PowerPC FXU

Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown
<span title="">2000</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 37th conference on Design automation - DAC &#39;00</a> </i> &nbsp;
The development of a PowerPC TM fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described.  ...  Manufactured in Motorola's 0.5−µm Complementary Gallium Arsenide process, the device operates from 0.9 to 1.9 V with a nominal frequency of 25 MHz at 1.3 V, dissipating 274 mW.  ...  We thank Cascade Design Automation, Mentor Graphics, MetaSoft and Fluence for the use of their CAD tools, which were critical to this project. CONTACT INFORMATION  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/337292.337760">doi:10.1145/337292.337760</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/DrakeBGKPGSB00.html">dblp:conf/dac/DrakeBGKPGSB00</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ykfhfiwq4fazvjqkcbf54d7u4i">fatcat:ykfhfiwq4fazvjqkcbf54d7u4i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20050319234210/http://www.sigda.org:80/Archives/ProceedingArchives/Dac/Dac2000/papers/2000/dac00/pdffiles/44_4.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b5/7d/b57d0840a43494bf2398bb63eb7f48a071f37349.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/337292.337760"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Execution cache-based microarchitecture for power-efficient superscalar processors

E. Talpes, D. Marculescu
<span title="">2005</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
By reusing instructions that are already decoded, reordered, and have their registers already renamed, the front end of the pipeline can be turned off for large periods of time with significant savings  ...  Our approach aims at limiting the growing amount of power used in a typical processor for dynamic optimizations (including out-of-order scheduling and register renaming).  ...  In these studies, the complexity of creating traces and storing them in an efficient structure is taken off of the critical execution path and placed after the Retire stage of the pipeline.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2004.840406">doi:10.1109/tvlsi.2004.840406</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/c7vxvdpnbfg3nfycflls552luu">fatcat:c7vxvdpnbfg3nfycflls552luu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060513015030/http://www.ece.cmu.edu:80/~dianam/journals/tvlsi05-2.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cc/77/cc77e2fc0ff6376ce1f5e8e135ebe1ed9629165d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2004.840406"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology

C.-K.V. Tien, K. Lewis, H.J. Greub, T. Tsen, J.F. McDonald
<span title="">1997</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
The wiring delays account for 42% of the critical path delay.  ...  Test results from a prototype fabrication run have demonstrated the operation of the ALU, the program counter, and the register file with delays below 6, 5, and 3.4 ns, respectively.  ...  Cappon, and J. Toole, whose appreciation of this work made its completion possible. Testing of F-RISC/I was made possible through the use of equipment at IBM.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.585228">doi:10.1109/92.585228</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rltlxvfphngl7bvlef7gvwhj3a">fatcat:rltlxvfphngl7bvlef7gvwhj3a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100612102538/http://www.ecse.rpi.edu/frisc/publications&amp;patents/Tien00585228.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/14/1d/141da498542bb3138045389549ec99bd03101286.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/92.585228"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Architecting processors to allow voltage/reliability tradeoffs

John Sartori, Rakesh Kumar
<span title="">2011</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/h3qjmo5xyfe6fcrh4fogxmkkiq" style="color: black;">Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES &#39;11</a> </i> &nbsp;
To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor.  ...  Recent work has proposed circuit and design-level optimizations [14, 15] that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs  ...  Caches and register files account for a large fraction of the critical paths of a processor [21] .  ... 
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Hardware-managed register allocation for embedded processors

Xiaotong Zhuang, Tao Zhang, Santosh Pande
<span title="">2004</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6dcohyzfhveypik7x4entpurlu" style="color: black;">Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES &#39;04</a> </i> &nbsp;
Finally, our results show slight improvement in the instructions per cycle counts (IPC) but significant power consumption reduction in the cache.  ...  Saving the encoding space leads to lower power consumption in the I-cache; on the other hand, harnessing more physical registers saves power in the memory subsystem and reduces latency as well.  ...  Obviously, eviction of the top of the heap is not on the critical path. At each branch instruction, we need to update the bb_to_live field for all entries in the current function level.  ... 
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Hardware-managed register allocation for embedded processors

Xiaotong Zhuang, Tao Zhang, Santosh Pande
<span title="2004-07-11">2004</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/xu5bk2lj5rbdxlx6222nw7tsxi" style="color: black;">SIGPLAN notices</a> </i> &nbsp;
Finally, our results show slight improvement in the instructions per cycle counts (IPC) but significant power consumption reduction in the cache.  ...  Saving the encoding space leads to lower power consumption in the I-cache; on the other hand, harnessing more physical registers saves power in the memory subsystem and reduces latency as well.  ...  Obviously, eviction of the top of the heap is not on the critical path. At each branch instruction, we need to update the bb_to_live field for all entries in the current function level.  ... 
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