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Improvement of detectability for CMOS floating gate defects in supply current test

Michinishi, Yokohira, Okamoto, Kobayashi, Hondo
<span title="">2003</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tquv56q3mbb3zbshmluyl4dp7a" style="color: black;">Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03</a> </i> &nbsp;
We already proposed a supply current test method for detecting floating gate defects in CMOS ICs.  ...  In this study, we propose one way to improve detectability of the method for the defects.  ...  Conclusion In this study, we proposed one way to improve the detectability of our test method for CMOS floating gate defects which make transistors conduct marginally and showed that they can be detected  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ats.2003.1250846">doi:10.1109/ats.2003.1250846</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ats/MichinishiYOKH03.html">dblp:conf/ats/MichinishiYOKH03</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cvkq2uonubgg7lpaurcarfgdbm">fatcat:cvkq2uonubgg7lpaurcarfgdbm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20171112024548/https://core.ac.uk/download/pdf/12528681.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/dd/bb/ddbbd68c13d13c6d298fbec03601e8cb01bebc03.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ats.2003.1250846"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

IDDQTesting Experiments for Various CMOS Logic Design Structures

A. Toukmaji, R. Helms, R. Makki, W. Mikhail, R. Toole
<span title="">1997</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dgruxbbpd5bedpkwsg4wfnroya" style="color: black;">VLSI design (Print)</a> </i> &nbsp;
The first study constitutes an assessment of the effectiveness of IDDQ(quiescent power supply current) in detecting transistor-level defects for three CMOS logic design styles.  ...  This study was carded out by designing, simulating, fabricating, and testing CMOS devices with built-in defects.  ...  Acknowledgments This work was supported, in part, by IBM-Charlotte.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/1997/51094">doi:10.1155/1997/51094</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2r7k4xynkbe3betpy4n6m3ekry">fatcat:2r7k4xynkbe3betpy4n6m3ekry</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190503162608/http://downloads.hindawi.com/journals/vlsi/1997/051094.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/89/26/89264244fe26e625c10b7d48c282d485fa48ae87.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/1997/51094"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

Gate Leakage Impact on Full Open Defects in Interconnect Lines

Daniel Arumi, Rosa Rodriguez-Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
<span title="">2011</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage.  ...  Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.  ...  Improvements in the detectability of such defects consist of applying logic test patterns for a SA1 (SA0) at the target node, requiring the neighboring lines to generate the maximum (minimum) pull-up (  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2010.2077315">doi:10.1109/tvlsi.2010.2077315</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rv4oepo3ujhi3odrq3yrydbm7m">fatcat:rv4oepo3ujhi3odrq3yrydbm7m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180723131455/https://upcommons.upc.edu/bitstream/handle/2117/12696/05638632.pdf;jsessionid=B2D32F88024F459B11980F045EA3FE86?sequence=1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/69/fb/69fb4276dd86ba458bcce673be0f1a81f8530752.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2010.2077315"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Maninder Kaur, Jasdeep Kaur
<span title="2018-06-01">2018</span> <i title="Institute of Advanced Engineering and Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sdt65w3c4jeojd2d4wr6rbkebe" style="color: black;">International Journal of Electrical and Computer Engineering (IJECE)</a> </i> &nbsp;
I<sub>DDQ</sub> testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit.  ...  A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under  ...  The steady state or quiescent current testing of CMOS integrated circuits is known to be very efficient for improving test quality [6] - [8] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.11591/ijece.v8i3.pp1467-1477">doi:10.11591/ijece.v8i3.pp1467-1477</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/pchb7apftzftde2krcw5sr2ktq">fatcat:pchb7apftzftde2krcw5sr2ktq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190429082342/http://www.iaescore.com/journals/index.php/IJECE/article/download/9058/8688" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7e/f6/7ef683e7a7cac934dd564f7a282e6cb75e159a9b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.11591/ijece.v8i3.pp1467-1477"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

ΔIDDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects

Rajiv Soundararajan, Ashok Srivastava, Siva Sankar Yellampalli
<span title="">2011</span> <i title="Scientific Research Publishing, Inc,"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7xp3xydesfgwbon56mgufqzvea" style="color: black;">Circuits and Systems</a> </i> &nbsp;
In this paper, we present the implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on  ...  A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.  ...  Introduction Quiescent current (I DDQ ) testing has become an effective and efficient testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging faults  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4236/cs.2011.23020">doi:10.4236/cs.2011.23020</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/beinmpkganbutl2ruldfusnwcy">fatcat:beinmpkganbutl2ruldfusnwcy</a> </span>
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Comparative Study of Fault Modeling for SG-mode and LP-mode INV

Archana Verma, Pushpa Giri
<span title="2016-03-28">2016</span> <i title="ESRSA Publications Pvt. Ltd."> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3j6n6lpsjndinobmibtprywohe" style="color: black;">International Journal of Engineering Research and</a> </i> &nbsp;
From a circuit testing viewpoint, it is unclear if CMOS fault models are absolute enough to model all defect in the FinFET circuits.  ...  FinFETs are expected to take the place of planner CMOS field-effect transistors (FETs) in the near future, due to their superior electrical characteristics.  ...  This behavior can be detected by guiding the supply current through IDDQ test [16] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.17577/ijertv5is030974">doi:10.17577/ijertv5is030974</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bkwc6zvwvve2lgaxnf4t42cly4">fatcat:bkwc6zvwvve2lgaxnf4t42cly4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200321234906/https://www.ijert.org/research/comparative-study-of-fault-modeling-for-sg-mode-and-lp-mode-inv-IJERTV5IS030974.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/af/7c/af7cc5d4708a51ce5c3010291e68d897604e55da.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.17577/ijertv5is030974"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Test Strategies for Multivoltage Designs [chapter]

Saqib Khursheed, Bashir M. Al-Hashimi
<span title="2009-08-13">2009</span> <i title="Springer US"> Power-Aware Testing and Test Strategies for Low Power Devices </i> &nbsp;
This chapter presents a coherent overview of recently reported research in testing strategies for multi-voltage designs including defect modelling, test generation and DFT solutions.  ...  Some manufacturing defects have Vdd-dependency, which implies defects can become active only at certain power supply setting, leading to reduced defect coverage.  ...  Ilia Polian (Albert-Ludwigs-University of Freiburg) for useful comments and EPSRC (U.K) for supporting this work under Grant EP/DO57663/1.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4419-0928-2_8">doi:10.1007/978-1-4419-0928-2_8</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sjivk55a2fboznqwcwoahghjiq">fatcat:sjivk55a2fboznqwcwoahghjiq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180719202351/https://eprints.soton.ac.uk/267331/1/Chapter_8.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/fa/b4/fab41d0372dd1bdbeb2426729b9bf05b9bb4c13a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4419-0928-2_8"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Single-ended SRAM with high test coverage and short test time

Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified.  ...  The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved. Index Terms-High test coverage, IFA-9, retention fault, singleended cell, SRAM.  ...  Quiescent supply current (IDDQ) testing is one effective technique of detecting both bridge faults and open faults in CMOS integrated circuits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/4.818928">doi:10.1109/4.818928</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jfmtudaejffdpgiceqd2b3gmqu">fatcat:jfmtudaejffdpgiceqd2b3gmqu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20030813082452/http://vlsi.ee.nsysu.edu.tw:80/papers/Jnl/Single-ended%20SRAM%20with%20high%20test%20coverage%20and%20short%20test%20time.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/9f/f09fd19b037160d008d187105171b65b0ca043d0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/4.818928"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Testability enhancement of a basic set of CMOS cells

M. Rullán, J. Oliver, C. Ferrer, F. C. Blom
<span title="">1994</span> <i title="Wiley"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tz7brgohvjfkjfb2hnawf234r4" style="color: black;">Quality and Reliability Engineering International</a> </i> &nbsp;
to improve cell layout can bring about great improvement in design.  ...  We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect).  ...  The short faults (including some floating gates) are very likely to appear and are detectable by means of IDDq measurements, which are assumed to be a good test technique in their detection.8, For example  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1002/qre.4680100406">doi:10.1002/qre.4680100406</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/lyysn4nwkvew3abz5k56zt2ive">fatcat:lyysn4nwkvew3abz5k56zt2ive</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706013231/http://doc.utwente.nl/71077/1/Rullan94test.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/66/77/66778a53ea4588ef21f77059865074901483645a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1002/qre.4680100406"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> wiley.com </button> </a>

Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

M. Ahmadi, K. Raahemifar
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l3azs6sc2zakpnimahudrlgqlu" style="color: black;">IEEE transactions on circuits and systems - 2, Analog and digital signal processing</a> </i> &nbsp;
It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and  ...  Index Terms-Concurrent testing, delay fault and stuck open fault testing, design for testability, fully testable CMOS circuit, VLSI testing. .  ...  Miller, Dean of Engineering at the University of Victoria, Canada, for his constructive and valuable comments.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/82.885134">doi:10.1109/82.885134</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/erlhh6kkmbaanlvljxhhhsgtki">fatcat:erlhh6kkmbaanlvljxhhhsgtki</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190220003801/http://pdfs.semanticscholar.org/1d26/e6aff15bf1bfb7e316db42bc71ac9c8e3301.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1d/26/1d26e6aff15bf1bfb7e316db42bc71ac9c8e3301.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/82.885134"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Technology and layout-related testing of static random-access memories

Kanad Chakraborty, Pinaki Mazumder
<span title="">1994</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dt5ooavfurcrfbcz432scm5wcu" style="color: black;">Journal of electronic testing</a> </i> &nbsp;
Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc.  ...  Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout.  ...  Testing of SRAMs by Monitoring IDD, the Dynamic Power Supply Current While IDDQ testing was fairly effective in detecting a general variety of CMOS defects not usually considered by functional testing,  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/bf00972519">doi:10.1007/bf00972519</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/icphzibj2vfwvgac5iohjpru64">fatcat:icphzibj2vfwvgac5iohjpru64</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170817202452/https://deepblue.lib.umich.edu/bitstream/handle/2027.42/43015/10836_2004_Article_BF00972519.pdf;sequence=1" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/76/f9/76f9e8e1511c274512aa8254ae3a1f2b4ef97846.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/bf00972519"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

On the Production Testing of Memristor Ratioed Logic (MRL) Gates

Ahmed Shukry Emara, Ahmed Hassan Madian, Hassanein Hamed Amer, Sherif Hassanein Amer, Mohamed Bakr Abdelhalim
<span title="">2016</span> <i title="Scientific Research Publishing, Inc,"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7xp3xydesfgwbon56mgufqzvea" style="color: black;">Circuits and Systems</a> </i> &nbsp;
This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates.  ...  Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates.  ...  Table 4 shows test results of detecting open faults in transistors M1 and M2 for the MRL NAND gate.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4236/cs.2016.710257">doi:10.4236/cs.2016.710257</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/x2nc7foulzfhla4cun3w3a5o2i">fatcat:x2nc7foulzfhla4cun3w3a5o2i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923041003/http://file.scirp.org/pdf/CS_2016081815575163.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/98/5a/985ad42a8ff17c077706f239c9b6bed54ff51acf.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4236/cs.2016.710257"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Delta-IDDQ Testing of a CMOS 12-Bit Charge Scaling DigitaltoAnalog Converter

Ashok Srivastava, Siva Yellampalli, Kalyan Golla
<span title="">2006</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/spkh3xuibzbhddsaffy2owumwa" style="color: black;">The ... Midwest Symposium on Circuits and Systems conference proceedings</a> </i> &nbsp;
I DDQ testing of CMOS ICs has proved to be very efficient for improving test quality.  ...  The test methodology based on the observation of quiescent current on power supply lines allows a good coverage of physical defects such as the gate oxide shorts, floating gates and bridging faults, which  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mwscas.2006.382094">doi:10.1109/mwscas.2006.382094</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gfategf6drdexgdwp7ukeosq24">fatcat:gfategf6drdexgdwp7ukeosq24</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200320063857/https://digitalcommons.lsu.edu/cgi/viewcontent.cgi?article=3808&amp;context=gradschool_theses" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/57/e3/57e3353e8290beddb9f1e0255dcb54108916c65d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mwscas.2006.382094"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Test consideration for nanometer-scale CMOS circuits

Kaushik Roy, T.M. Mak, K.-T. Cheng
<span title="">2006</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hkpx3vsnhrfb7jh6hlwads7olq" style="color: black;">IEEE Design &amp; Test of Computers</a> </i> &nbsp;
Acknowledgments This work was supported in part by the MARCO/DARPA Gigascale Systems Research Center, the National Science Foundation, IBM, and Intel.  ...  The twoparameter test technique improves the effectiveness of I DDQ testing for single-threshold, fast CMOS ICs.  ...  The subthreshold current (I 2 ) is another dominant component of leakage and is even important in the active mode of Test Consideration for Nanometer-Scale CMOS Circuits Editor's note: Test technology  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2006.52">doi:10.1109/mdt.2006.52</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ichk4podpvh4diznseqjwup7ti">fatcat:ichk4podpvh4diznseqjwup7ti</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100706123316/http://cadlab.ece.ucsb.edu/~web_adim/publication/2006/Test%20Consideration_Tim.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/eb/52/eb52b7ac5e0944efad76522aec399a72c56b0633.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mdt.2006.52"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Backside localization of open and shorted IC interconnections

E.I. Jr. Cole, P. Tangyunyong, D.L. Barton
<span title="">1998</span> <i title="IEEE"> 1998 IEEE International Reliability Physics Symposium Proceedings 36th Annual (Cat No 98CH36173) RELPHY-98 </i> &nbsp;
Images are produced by monitoring the voltage changes across a constant current supply used to power the IC as the laser beam is scanned across the sample.  ...  A new failure analysis technique has been developed for backside and frontside localization of open and shorted interconnections on ICs.  ...  For very low power CMOS devices, IC power changes corresponding to a supply current increase of 100 pA for a constant supply voltage have been shown to produce a 2 V supply voltage decrease for constant  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/relphy.1998.670462">doi:10.1109/relphy.1998.670462</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/632hzrrgufcx5aovdy2lxzpfii">fatcat:632hzrrgufcx5aovdy2lxzpfii</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170814171240/https://digital.library.unt.edu/ark:/67531/metadc699328/m2/1/high_res_d/629451.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/11/a6/11a6521414d55870a8ed6267dd973519aabf6371.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/relphy.1998.670462"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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