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Hybrid-compiled simulation
2009
ACM Transactions on Embedded Computing Systems
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This article presents a hybrid instruction-set-compiled simulation (HISCS) technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation ...
This article makes two important contributions: (i) it improves the interpretive simulation performance by applying compiled simulation at the instruction level using a novel template-customization technique ...
This article makes two primary contributions in design of fast and flexible instruction-set simulation. ...
doi:10.1145/1509288.1509292
fatcat:rlcve75yercsxi3egzazawsp54
Instruction set compiled simulation
2003
Proceedings of the 40th conference on Design automation - DAC '03
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This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. ...
Our instruction set compiled simulation (IS-CS) technique delivers upto 40% performance improvement over the best known published result that has the flexibility of interpretive simulation. ...
INSTRUCTION SET COMPILED SIMU-LATION We developed the instruction set compiled simulation (IS-CS) technique with the intention of combining the full flexibility of interpretive simulation with the speed ...
doi:10.1145/775832.776026
dblp:conf/dac/ReshadiMD03
fatcat:nlxudj6tcva2dkandc7ponu7kq
Generation of Executable Representation for Processor Simulation with Dynamic Translation
2008
2008 International Conference on Computer Science and Software Engineering
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Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. ...
This paper presents a simulator where we have developed and integrated three techniques: an interpretive simulator and two variants of dynamic translation. ...
Different simulators use different kinds of intermediate representation (IR) to improve the performance or to increase modularity and flexibility. ...
doi:10.1109/csse.2008.635
dblp:conf/csse/SongHHJ08
fatcat:nvtbs6rv6fej5kkbzob3sttl24
Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach
2006
Proceedings of the Design Automation & Test in Europe Conference
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This paper presents a framework that quickly generates fast and flexible instruction-set simulators from a specification based on a C-like architecture-description language. ...
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. ...
Acknowledgments This research is partially supported by a UROP Faculty Matching Grant from Boston University. We thank Prof. ...
doi:10.1109/date.2006.244006
dblp:conf/date/DErricoQ06
fatcat:p5kaw4xczzei3dwmhztyktku7a
A universal technique for fast and flexible instruction-set architecture simulation
2002
Proceedings - Design Automation Conference
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This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. ...
Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. ...
-Multiple Instruction Sets Compiled simulation is qualified by an enormous memory usage. ...
doi:10.1145/513918.513927
dblp:conf/dac/NohlBSLMH02
fatcat:d2qvbwumrbco7mx3xoofkqbyba
A universal technique for fast and flexible instruction-set architecture simulation
2002
Proceedings - Design Automation Conference
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This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. ...
Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. ...
-Multiple Instruction Sets Compiled simulation is qualified by an enormous memory usage. ...
doi:10.1145/513926.513927
fatcat:whp3ai2hineirn5slk5skttb6e
A universal technique for fast and flexible instruction-set architecture simulation
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. ...
Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. ...
-Multiple Instruction Sets Compiled simulation is qualified by an enormous memory usage. ...
doi:10.1109/dac.2002.1012588
fatcat:yfk6lu2hyndejab5espnxgdpyi
A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. ...
Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. ...
-Multiple Instruction Sets Compiled simulation is qualified by an enormous memory usage. ...
doi:10.1109/tcad.2004.836734
fatcat:cmokreeppbgzzppn6fipxfkzrq
Memory access optimizations in instruction-set simulators
2005
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05
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Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. ...
To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. ...
Figure 3 shows the flow of a fast and flexible interpretive simulation. The flexibility is maintained since the simulation engine still fetches and executes one target instruction at a time. ...
doi:10.1145/1084834.1084895
dblp:conf/codes/ReshadiM05
fatcat:fyunmntgtvh5xpjjbk4rwnr3dy
Shade: a fast instruction-set simulator for execution profiling
1994
Performance Evaluation Review
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This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. ...
Efficiency is achieved by dynamically compiling and caching code to simulate and trace the application program. ...
This work was supported by Sun Microsystems, NSF #CDA-8619-663 and NSF PYI #MIP-9058-439. ...
doi:10.1145/183019.183032
fatcat:ioneaoyuuncyxfpmixoqikr3vy
Shade: a fast instruction-set simulator for execution profiling
1994
Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems - SIGMETRICS '94
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This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. ...
Efficiency is achieved by dynamically compiling and caching code to simulate and trace the application program. ...
This work was supported by Sun Microsystems, NSF #CDA-8619-663 and NSF PYI #MIP-9058-439. ...
doi:10.1145/183018.183032
dblp:conf/sigmetrics/CmelikK94
fatcat:n4h5zab7unerxas4g4mvggyhsi
Shade: A Fast Instruction-Set Simulator for Execution Profiling
[chapter]
1995
Fast Simulation of Computer Architectures
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The file type is application/pdf.
This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. ...
Efficiency is achieved by dynamically compiling and caching code to simulate and trace the application program. ...
This work was supported by Sun Microsystems, NSF #CDA-8619-663 and NSF PYI #MIP-9058-439. ...
doi:10.1007/978-1-4615-2361-1_2
fatcat:vipxmqbxfndebi2etvkpeheuka
Fast functional simulation with a dynamic language
2012
2012 IEEE Conference on High Performance Extreme Computing
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Simulation of large computational systems-on-a-chip (SoCs) is increasing challenging as the number and complexity of components is scaled up. ...
We demonstrate a fresh approach to ISS that achieves performance comparable to a fast dynamic binary translator by exploiting recent advances in just-in-time (JIT) compilers for dynamic languages, such ...
ACKNOWLEDGMENT The authors would like to thank LuaJIT creator Mike Pall for his informative postings about LuaJIT optimization in general, and tail-call optimizations as a basis for efficient simulator ...
doi:10.1109/hpec.2012.6408664
dblp:conf/hpec/SteeleB12
fatcat:wpod4ef4s5flld2knbpwfb4dja
Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor
2005
ETRI Journal
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The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. ...
We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. ...
Using the simulator and compiler, of which the processor is composed of the basic instruction set, the application software programmed in C/C++ is compiled and analyzed. ...
doi:10.4218/etrij.05.0905.0001
fatcat:ohemqmxb6fa5foxqnfljzdq7vm
A Flexible Datapath Interconnect for Embedded Applications
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
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For an FFT benchmark, the introduction of a flexible interconnect reduces the total execution time by 16%. ...
We investigate the effects of introducing a flexible interconnect into an exposed datapath. ...
Compiler The current version of the FlexCore compiler takes MIPS assembly code as input and generates a set of so-called Native ISA (N-ISA) instructions, which correspond to the instructions for the exposed ...
doi:10.1109/isvlsi.2007.4
dblp:conf/isvlsi/SjalanderLB07
fatcat:qcb2peneirfarps3s6jkju3qae
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