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The implicit set paradigm: A new approach to finite state system verification

1995
*
Formal methods in system design
*

This paper presents a new

doi:10.1007/bf01383965
fatcat:hoaxmjw32rb2tfnowrd6gvn7di
*state**of*the art in the field*of**finite**state*system verification. The paradigm*of*this approach is to represent and to manipulate these systems in an*implicit*way. ... The computational costs*of*the verification procedures*using*this paradigm depend on the costs*of*the operations performed on this*implicit*representation instead*of*the number*of**states*and transitions ...*finite**state**machines*[24] . ...##
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A comprehensive approach to the partial scan problem using implicit state enumeration

2002
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

For large circuits,

doi:10.1109/tcad.2002.1013894
fatcat:bnmgm2qa5jdxngollxvfsrlfgu
*implicit**state**enumeration*becomes infeasible because*of*computer memory and time limitations. ... Our model*uses**implicit*techniques for FSM traversal to identify non-controllable*state*registers. ...*enumeration*techniques*using**BDDs*. ...##
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An implicit formulation for exact BDD minimization of incompletely specified functions
[chapter]

1997
*
VLSI: Integrated Systems on Silicon
*

specified

doi:10.1007/978-0-387-35311-1_26
fatcat:q3h3jn5fvfes7jheuq5m3uia6y
*finite**state**machines*. ... Here we show that the*BDD*minimization problem can be formulated as a binate covering problem and solved*using**implicit**enumeration*techniques similar to the ones*used*in the reduction*of*incompletely ... exact algorithms for the reduction*of*incompletely specified*finite**state**machines*(ISFSM) (Kam, Villa, Brayton & Vincentelli 1994 ). ...##
###
Asymptotic Representation of Discrete Groups
[chapter]

1998
*
Lie Groups and Lie Algebras
*

This tutorial paper discusses the known representations based on Binary Decision Diagrams (

doi:10.1007/978-94-011-5258-7_19
fatcat:7zdslkcrvrdyboc7xfwtqb3x7m
*BDDs*) for various types*of*discrete objects: incompletely specified functions, sets,*finite**state**machines*, binary ... The last type*of*objects, information measures, constitute a promising approach to problem solving in a number*of*areas, including decomposition*of*discrete functions and*finite**state**machines*. ... Our implementation*of**implicit*algorithms is based on*state*-*of*-the-art Binary Decision Diagram package BuDDy, Release 1.7 [34] , by Jørn Lind-Nielsen, Department*of*Information Technology, Technical University ...##
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A comparison of Presburger engines for EFSM reachability
[chapter]

1998
*
Lecture Notes in Computer Science
*

*Implicit*

*state*

*enumeration*for extended

*finite*

*state*

*machines*relies on a decision procedure for Presburger arithmetic. ... While the raw speed

*of*each

*of*these two packages can be superior to the other by a factor

*of*50 or more, we found the asymptotic performance

*of*Shasta to be equal or superior to that

*of*Omega for the ... Acknowledgments We thank Kurt Keutzer for suggesting to

*us*the

*use*

*of*Presburger arithmetic for analyzing EFSMs, and Adnan Aziz for modifying VIS to support EFSMs. ...

##
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Verification of interacting sequential circuits

1990
*
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
*

The problem

doi:10.1145/123186.123260
dblp:conf/dac/GhoshDN90
fatcat:dkcnthurtnfc3hngk33hpyhmoi
*of*verifying the equivalence*of*interacting*finite**state**machines*(FSMs) described a t the logic level is addressed. ... The input as well as the*state*space is implicitly*enumerated*through a process*of*repeated cube intersections to generate the*State*Transition Graph (STG). ... Verification*of*Single*Finite**State**Machines*Combinational logic circuits have been verified*using*an*enumeration*-simulation approach. ...##
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Permissible observability relations in FSM networks

1994
*
Proceedings of the 31st annual conference on Design automation conference - DAC '94
*

We demonstrate that output don't care sequences for a component can be expressed

doi:10.1145/196244.196613
dblp:conf/dac/WangB94
fatcat:ukxqusfhbvfjnhhbvyuhevv25m
*using*a set*of*observability relations given that its*state*transition function is kept unchanged. ... We briefly discuss the exploitation*of*permissible observability relations in*state*minimization, circuit implementation and signal encoding. ... Also special thanks to Szu-Tsung Cheng and Thomas Shiple for helpful discussions on the*BDD*package. ...##
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FSM decomposition by direct circuit manipulation applied to low power design

2000
*
Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00
*

This way, we do not require the STG, either explicit or

doi:10.1145/368434.368678
dblp:conf/aspdac/MonteiroO00
fatcat:rkwfbocfhfcxjhnqvj2povdswm
*implicit*, thus further avoiding the limitations imposed by the*use**of**BDDs*. ... In particular, recent work has shown that significant power reductions are possible with techniques based on*finite**state**machine*(FSM) decomposition. ... BASIC DEFINITIONS We*use*the standard definition*of**finite**state**machines*: Definition II.1 A*finite**state**machine*is a tuple M Q q 0 where / 0 is a*finite*set*of*input symbols, / 0 is a*finite*set*of*output ...##
###
Implicit enumeration of strongly connected components and an application to formal verification

2000
*
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*

Experimental results show that our new bad cycle detection algorithm is typically significantly faster than the

doi:10.1109/43.875347
fatcat:po47lbef2fecng43tgn6bfawn4
*state*-*of*-the-art [1], sometimes by more than a factor*of*ten. ... Experimental results suggest that the algorithm dramatically outperforms the only existing*implicit*method which must compute the transitive closure*of*the adjacency-matrix*of*the graphs. ... Somenzi*of*the University*of*Colorado at Boulder for insightful and motivating discussions regarding ...##
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Testability analysis and behavioral testing of the Hopfield neural paradigm

1998
*
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
*

In this paper, we consider the case

doi:10.1109/92.711323
fatcat:l4udwlbgffc2douehrhygloqym
*of*Hopfield's networks, as the simplest example*of*networks with feedback loops. A behavioral error model based on*finite*-*state**machines*(FSM's) is introduced. ... To perform the second step the number*of**states*in*US*must be enumeratable. This is not restrictive since these*states*constitute the test sequence that must have*finite*size to be*of*practical*use*. ... Set*of**states**of*the*machine*(*states*being coded as vectors*of*the Hopfield network). Input alphabet defined as the set*of*input vectors*used*to force initial*states*. ...##
###
State-based power analysis for systems-on-chip

2003
*
Proceedings of the 40th conference on Design automation - DAC '03
*

Given the power

doi:10.1145/775832.775992
dblp:conf/dac/BergamaschiJ03
fatcat:ade3ezxfdzhgbchwf3tdv6lko4
*state**machines*for individual cores, this work defines the product power*state**machine*for the whole SoC and*uses*formal symbolic simulation algorithms for traversing and computing the ... minimum and maximum power dissipated by sets*of*power*states*in the SoC. ... ACKNOWLEDGMENTS The authors would like to thank Geert Janssen for help with the*BDD*package and Youngsoo Shin and Indira Nair for help with power simulation*of*specific scenarios. ...
This has been facilitated by the

doi:10.1145/196244.196467
dblp:conf/dac/AzizBCHKKRSSTWBS94
fatcat:rle757zd4jccxckdiw6zrwus2m
*use**of*binary decision diagrams (*BDDs*). This paper describes the essential features*of*HSIS, a*BDD*-based environment for formal verification: 1. ... Support for*state*minimization*using*bisimulation and similar techniques. HSIS allows*us*to experiment with formal verification techniques on a variety*of*design problems. ... There are two main methods to perform this exploration-explicit methods and*implicit*methods (based on*BDDs*).*Implicit*methods manipulate sets*of**states*at a time. ...##
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Symbolic model checking of declarative relational models

2006
*
Proceeding of the 28th international conference on Software engineering - ICSE '06
*

We built a

doi:10.1145/1134285.1134329
dblp:conf/icse/ChangJ06
fatcat:2nt42vnnrrg3bopck7qhf44qkm
*BDD*-based model checker for the language, and successfully verified a straightforward model*of*the dependency algorithm in Apache Ant for up to 5 nodes. ... By allowing a mixture*of*both, and by allowing parts*of*the model to be described declaratively rather than imperatively, the programmer has the freedom to model each part*of*the system differently,*using*... Since the*state*space is*finite*, every branch*of*the tree eventually leads to a previously visited*state*. Therefore, this infinite tree*of**states*can be viewed as a*finite*Kripke structure. ...##
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Automatic verification of pipelined microprocessors

1994
*
Proceedings of the 31st annual conference on Design automation conference - DAC '94
*

We show that only a small number

doi:10.1145/196244.196577
dblp:conf/dac/BhagwatiD94
fatcat:ruzgdeilirb7xolgrba24hjo2e
*of*cycles, rather than exhaustive*state*transition graph traversal and*state**enumeration*, have to be simulated for each*machine*to verify whether the implementation is ... We*use*symbolic simulation*of*the specification and implementation to verify their functional equivalence. ... This involved exhaustively traversing the*State*Transition Graph*of*the product*of*the two*machines*,*using**implicit**state**enumeration*techniques. ...##
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An Abstract Reachability Approach by Combining HOL Induction and Multiway Decision Graphs

2009
*
Journal of Computer Science and Technology
*

The MDG reachability algorithm is then defined as a conversion that

doi:10.1007/s11390-009-9205-8
fatcat:6a6dssulk5exrimvprokwapmoy
*uses*our MDG theory within HOL. ... In this paper, we provide a necessary infrastructure to define an abstract*state*exploration in the HOL theorem prover. ... An abstract description*of*a*state**machine*M is a tuple D = (X, Y, Z, Y , IS , Tr , Or ), where: X:*finite*set*of*input variables; Y:*finite*set*of**state*variables; Z:*finite*set*of*output variables; Y ...
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