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The implicit set paradigm: A new approach to finite state system verification

O. Coudert, J. C. Madre
1995 Formal methods in system design  
This paper presents a new state of the art in the field of finite state system verification. The paradigm of this approach is to represent and to manipulate these systems in an implicit way.  ...  The computational costs of the verification procedures using this paradigm depend on the costs of the operations performed on this implicit representation instead of the number of states and transitions  ...  finite state machines [24] .  ... 
doi:10.1007/bf01383965 fatcat:hoaxmjw32rb2tfnowrd6gvn7di

A comprehensive approach to the partial scan problem using implicit state enumeration

P. Kalla, M. Ciesielski
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
For large circuits, implicit state enumeration becomes infeasible because of computer memory and time limitations.  ...  Our model uses implicit techniques for FSM traversal to identify non-controllable state registers.  ...  enumeration techniques using BDDs.  ... 
doi:10.1109/tcad.2002.1013894 fatcat:bnmgm2qa5jdxngollxvfsrlfgu

An implicit formulation for exact BDD minimization of incompletely specified functions [chapter]

Arlindo L. Oliveira, Luca P. Carloni, Tiziano Villa, Alberto Sangiovanni-Vincentelli
1997 VLSI: Integrated Systems on Silicon  
specified finite state machines.  ...  Here we show that the BDD minimization problem can be formulated as a binate covering problem and solved using implicit enumeration techniques similar to the ones used in the reduction of incompletely  ...  exact algorithms for the reduction of incompletely specified finite state machines (ISFSM) (Kam, Villa, Brayton & Vincentelli 1994 ).  ... 
doi:10.1007/978-0-387-35311-1_26 fatcat:q3h3jn5fvfes7jheuq5m3uia6y

Asymptotic Representation of Discrete Groups [chapter]

Alexander S. Mishchenko, Noor Mohammad
1998 Lie Groups and Lie Algebras  
This tutorial paper discusses the known representations based on Binary Decision Diagrams (BDDs) for various types of discrete objects: incompletely specified functions, sets, finite state machines, binary  ...  The last type of objects, information measures, constitute a promising approach to problem solving in a number of areas, including decomposition of discrete functions and finite state machines.  ...  Our implementation of implicit algorithms is based on state-of-the-art Binary Decision Diagram package BuDDy, Release 1.7 [34] , by Jørn Lind-Nielsen, Department of Information Technology, Technical University  ... 
doi:10.1007/978-94-011-5258-7_19 fatcat:7zdslkcrvrdyboc7xfwtqb3x7m

A comparison of Presburger engines for EFSM reachability [chapter]

Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan
1998 Lecture Notes in Computer Science  
Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic.  ...  While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we found the asymptotic performance of Shasta to be equal or superior to that of Omega for the  ...  Acknowledgments We thank Kurt Keutzer for suggesting to us the use of Presburger arithmetic for analyzing EFSMs, and Adnan Aziz for modifying VIS to support EFSMs.  ... 
doi:10.1007/bfb0028752 fatcat:tmri4cylxrbuze3q7sb6k6c36a

Verification of interacting sequential circuits

Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
The problem of verifying the equivalence of interacting finite state machines (FSMs) described a t the logic level is addressed.  ...  The input as well as the state space is implicitly enumerated through a process of repeated cube intersections to generate the State Transition Graph (STG).  ...  Verification of Single Finite State Machines Combinational logic circuits have been verified using an enumeration-simulation approach.  ... 
doi:10.1145/123186.123260 dblp:conf/dac/GhoshDN90 fatcat:dkcnthurtnfc3hngk33hpyhmoi

Permissible observability relations in FSM networks

Huey-Yih Wang, Robert K. Brayton
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
We demonstrate that output don't care sequences for a component can be expressed using a set of observability relations given that its state transition function is kept unchanged.  ...  We briefly discuss the exploitation of permissible observability relations in state minimization, circuit implementation and signal encoding.  ...  Also special thanks to Szu-Tsung Cheng and Thomas Shiple for helpful discussions on the BDD package.  ... 
doi:10.1145/196244.196613 dblp:conf/dac/WangB94 fatcat:ukxqusfhbvfjnhhbvyuhevv25m

FSM decomposition by direct circuit manipulation applied to low power design

José C. Monteiro, Arlindo L. Oliveira
2000 Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00  
This way, we do not require the STG, either explicit or implicit, thus further avoiding the limitations imposed by the use of BDDs.  ...  In particular, recent work has shown that significant power reductions are possible with techniques based on finite state machine (FSM) decomposition.  ...  BASIC DEFINITIONS We use the standard definition of finite state machines: Definition II.1 A finite state machine is a tuple M Q q 0 where / 0 is a finite set of input symbols, / 0 is a finite set of output  ... 
doi:10.1145/368434.368678 dblp:conf/aspdac/MonteiroO00 fatcat:rkwfbocfhfcxjhnqvj2povdswm

Implicit enumeration of strongly connected components and an application to formal verification

Aiguo Xie, P.A. Beerel
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Experimental results show that our new bad cycle detection algorithm is typically significantly faster than the state-of-the-art [1], sometimes by more than a factor of ten.  ...  Experimental results suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of the adjacency-matrix of the graphs.  ...  Somenzi of the University of Colorado at Boulder for insightful and motivating discussions regarding  ... 
doi:10.1109/43.875347 fatcat:po47lbef2fecng43tgn6bfawn4

Testability analysis and behavioral testing of the Hopfield neural paradigm

C. Alippi, F. Fummi, V. Piuri, M. Sami, D. Sciuto
1998 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we consider the case of Hopfield's networks, as the simplest example of networks with feedback loops. A behavioral error model based on finite-state machines (FSM's) is introduced.  ...  To perform the second step the number of states in US must be enumeratable. This is not restrictive since these states constitute the test sequence that must have finite size to be of practical use.  ...  Set of states of the machine (states being coded as vectors of the Hopfield network). Input alphabet defined as the set of input vectors used to force initial states.  ... 
doi:10.1109/92.711323 fatcat:l4udwlbgffc2douehrhygloqym

State-based power analysis for systems-on-chip

Reinaldo A. Bergamaschi, Yunjian W. Jiang
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the  ...  minimum and maximum power dissipated by sets of power states in the SoC.  ...  ACKNOWLEDGMENTS The authors would like to thank Geert Janssen for help with the BDD package and Youngsoo Shin and Indira Nair for help with power simulation of specific scenarios.  ... 
doi:10.1145/775832.775992 dblp:conf/dac/BergamaschiJ03 fatcat:ade3ezxfdzhgbchwf3tdv6lko4


A. Aziz, S. Tasiran, H.-Y. Wang, R. K. Brayton, A. L. Sangiovanni-Vincentelli, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S. C. Krishnan, R. K. Ranjan, T. R. Shiple (+1 others)
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a BDD-based environment for formal verification: 1.  ...  Support for state minimization using bisimulation and similar techniques. HSIS allows us to experiment with formal verification techniques on a variety of design problems.  ...  There are two main methods to perform this exploration-explicit methods and implicit methods (based on BDDs). Implicit methods manipulate sets of states at a time.  ... 
doi:10.1145/196244.196467 dblp:conf/dac/AzizBCHKKRSSTWBS94 fatcat:rle757zd4jccxckdiw6zrwus2m

Symbolic model checking of declarative relational models

Felix Sheng-Ho Chang, Daniel Jackson
2006 Proceeding of the 28th international conference on Software engineering - ICSE '06  
We built a BDD-based model checker for the language, and successfully verified a straightforward model of the dependency algorithm in Apache Ant for up to 5 nodes.  ...  By allowing a mixture of both, and by allowing parts of the model to be described declaratively rather than imperatively, the programmer has the freedom to model each part of the system differently, using  ...  Since the state space is finite, every branch of the tree eventually leads to a previously visited state. Therefore, this infinite tree of states can be viewed as a finite Kripke structure.  ... 
doi:10.1145/1134285.1134329 dblp:conf/icse/ChangJ06 fatcat:2nt42vnnrrg3bopck7qhf44qkm

Automatic verification of pipelined microprocessors

Vishal Bhagwati, Srinivas Devadas
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
We show that only a small number of cycles, rather than exhaustive state transition graph traversal and state enumeration, have to be simulated for each machine to verify whether the implementation is  ...  We use symbolic simulation of the specification and implementation to verify their functional equivalence.  ...  This involved exhaustively traversing the State Transition Graph of the product of the two machines, using implicit state enumeration techniques.  ... 
doi:10.1145/196244.196577 dblp:conf/dac/BhagwatiD94 fatcat:ruzgdeilirb7xolgrba24hjo2e

An Abstract Reachability Approach by Combining HOL Induction and Multiway Decision Graphs

Sa'ed Abed, Otmane Ait Mohamed, Ghiath Al-Sammane
2009 Journal of Computer Science and Technology  
The MDG reachability algorithm is then defined as a conversion that uses our MDG theory within HOL.  ...  In this paper, we provide a necessary infrastructure to define an abstract state exploration in the HOL theorem prover.  ...  An abstract description of a state machine M is a tuple D = (X, Y, Z, Y , IS , Tr , Or ), where: X: finite set of input variables; Y: finite set of state variables; Z: finite set of output variables; Y  ... 
doi:10.1007/s11390-009-9205-8 fatcat:6a6dssulk5exrimvprokwapmoy
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