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TOWARDS AUTOMATED ERROR LOCALIZATION IN C PROGRAMS WITH LOOPS
2019
System Informatics
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The most recent trends in the C-light verification system are MetaVCG, semantic labels appropriate for verification condition (VC) explanation and symbolic method of definite iterations. ...
MetaVCG takes a C-light program together with some Hoare's logic and produces on-the-fly a VC generator (VCG), which in turn processes the input program. ...
Introduction The C-light project [12] corresponds to the mainstream architecture of modern verification systems. ...
doi:10.31144/si.2307-6410.2019.n14.p31-44
fatcat:eq3zns7morcflj2q2pkva3pgqi
CELL: A Compositional Verification Framework
[chapter]
2013
Lecture Notes in Computer Science
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., compositional verification paradigms, learning algorithms and model checking methods to support various state-of-the-art compositional verification approaches. ...
The experimental results show that the performance of these model checkers can offer similar or often better performance compared to the state-of-the-art verification tools. ...
Implementation and Evaluation CELL is implemented on Microsoft .NET framework via C # language. Starting from 2011, the latest version 0.3 of CELL has 54K LOC. ...
doi:10.1007/978-3-319-02444-8_38
fatcat:wzzt6aawo5en5ihb24rslt7bkq
Intelligent Systems and Formal Methods in Software Engineering
2006
IEEE Intelligent Systems
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Confidence in the correctness of the proof is very high because it has been generated and checked automatically by computer. ...
Our understanding of the concept of a proof goes back to the Greek philosophers Pythagoras and Aristotle. ...
In the light of certification, this is increasingly important. ...
doi:10.1109/mis.2006.117
fatcat:e3gffxrewbhubelnmkv7rvrf7i
Applying Formal Methods to Networking: Theory, Techniques, and Applications
2015
IEEE Communications Surveys and Tutorials
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This has also led to a great resurgence in interest of applying formal methods to specification, verification, and synthesis of networking protocols and applications. ...
In this paper, we present a self-contained tutorial of the formidable amount of work that has been done in formal methods, and present a survey of its applications to networking. ...
In another work, Bishop et al. [184] have proposed symbolic evaluation testing of TCP implementation against a HOL specification.
C. ...
doi:10.1109/comst.2014.2345792
fatcat:oc6l6pn4tnddjbbr5v4gbbuycq
Virtual Integration of Real-Time Systems Based on Resource Segregation Abstraction
[chapter]
2014
Lecture Notes in Computer Science
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Therefore, engineers can negotiate specifications of the individual components a priori, knowing that no integration issues will occur due to shared resource usage. ...
It is thus important to have rigorous analysis techniques for determining timing properties of such systems. ...
The contribution of this paper will help to reduce verification complexity for the application of computational methods. ...
doi:10.1007/978-3-319-10512-3_15
fatcat:j6tkgvbzvfdmdkfnuhxqqhctee
Securing ZigBee Commercial Communications Using Constellation Based Distinct Native Attribute Fingerprinting
2018
Security and Communication Networks
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With MDA training thresholds set to achieve a True Verification Rate (TVR) of TVR = 95% for authorized network devices, the collective rogue device detection results for SNR ≥ 12 dB include average burst-by-burst ...
This work provides development of Constellation Based DNA (CB-DNA) Fingerprinting for use in systems employing quadrature modulations and includes network protection demonstrations for ZigBee offset quadrature ...
(1) implementation details of commercial methods are generally proprietary and (2) the statistical effectiveness of such methods is generally unpublished. ...
doi:10.1155/2018/1489347
fatcat:auxrcslysjhhzkcqcegtrbnrqq
Run-Time Security Traceability for Evolving Systems
2010
Computer journal
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The proposed method has been applied to the Java-based implementation JESSIE of the Internet security protocol SSL, in which a security weakness was detected and fixed using our approach. ...
A lot of vulnerabilities have been found in current software systems both at the specification and the implementation levels. ...
Acknowledgements Discussions with Martin Leucker about a draft of this paper are gratefully acknowledged, as well as constructive comments by the reviewers which helped improving the presentation significantly ...
doi:10.1093/comjnl/bxq042
fatcat:5atpkvz7d5gufpvphwjno65lsa
Computer Assisted Reasoning
2009
Journal of automated reasoning
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More recently, as a joint project with Birtwistle at Leeds, a model of an ARM instruction set architecture was shown to be correctly implemented by a model of the ARM6 microarchitecture [10, 11] . ...
and symbolic analysis tools. ...
doi:10.1007/s10817-009-9144-7
fatcat:rd5iyn6gw5canbyhgz4gfxt2yi
Efficient verification of railway infrastructure designs against standard regulations
2017
Formal methods in system design
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We apply our tool chain in a Norwegian railway project, the upgrade of the Arna railway station. ...
The work uses as case study the software and the design used in the Arna-Fløen upgrade project, 2 a major infrastructure activity of the Norwegian railway system, with planned completion in 2020. ...
, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. ...
doi:10.1007/s10703-017-0281-z
fatcat:pjyzayz77jgrnhazr7afj6l3yy
A Development of Visualization Technology through AR-Based Design Checklist Connection
2022
Applied Sciences
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Since the initial design review has the effect of minimizing the design changes needed in the later stages of an architectural project, a process of collaboration between architects, clients, and engineers ...
The efficiency of the design checklist linkage technology and visualization function developed in this study was verified in the pilot project. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/app12126126
fatcat:bakfrqaphragvclfahw6a6xgsy
Formal verification of hardware correctness: introduction and survey of current research
1988
Computer
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In particular, we would like to thank Dominique Borrione, Mario Barbacci, Hans Eveking, and the referees for their help in reviewing the article, their suggestions, and their valuable cooperation. ...
Acknowledgments We are grateful to all those people who kindly provided us with the papers, reports, and material used throughout this article. ...
The specifications, represented by input/output assertions in first-order predicates, tie the method to formal verification. ...
doi:10.1109/2.65
fatcat:dn5xh3m4gbacfffc5ogxybxbjm
Verifying the adaptation behavior of embedded systems
2006
Proceedings of the 2006 international workshop on Self-adaptation and self-managing systems - SEAMS '06
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This allows to extract the relevant information in a form that can be directly used for verification. ...
Formal verification, which is routinely applied in safety-critical applications, must therefore consider not only temporal and functional properties of a system, but also its ability to dynamically adapt ...
Model Checking Beryl is a symbolic model checker for the verification of finite and infinite state systems. ...
doi:10.1145/1137677.1137681
dblp:conf/icse/0001ST06
fatcat:43vlhfyrhjfgjh7uhp4nq4dwxm
Simplifying the Formal Verification of Safety Requirements in Zone Controllers Through Problem Frames and Constraint-Based Projection
2018
IEEE transactions on intelligent transportation systems (Print)
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In this paper, we aim to reduce the state space of formal verification problems in Zone Controller, a sub-system of a typical CBTC. ...
Our industrial case study demonstrates the feasibility though an evaluation, confirming that these two methods are effective in reducing the state spaces of complex verification problems in this application ...
ACKNOWLEDGMENT The authors would like to thank Liangyu Chen and Min Zhang from East China Normal University for their great help during the development of the algorithms implementation and proof of the ...
doi:10.1109/tits.2018.2869633
fatcat:hu2o2hh6nfewvkvk25orgm5sxq
A Unified Model Based Framework for the Simplified Execution of Static and Dynamic Assertion Based Verification
2020
IEEE Access
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The significance of the MODEVES framework is established through several case studies and the quantitative analysis shows an improvement of almost 100% in design productivity, as compared to the conventional ...
Furthermore, the dynamic verification support is provided through some traditional languages (like C, Verilog) where the advanced ABV features cannot be exploited. ...
Java Services: It implements the logic of transformation rules (Section III-B, Section III-C and Section III-D). ...
doi:10.1109/access.2020.2999544
fatcat:qequiagqpjc63hnuprcn6b2fu4
A flexible formal verification framework for industrial scale validation
2011
Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)
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In recent years, leading microprocessor companies have made huge investments to improve the reliability of their products. ...
This paper describes the formal verification framework we have built on top of publicly-available tools. ...
Niklas Een gave us an early access to Berkeley ZZ and provided the means to integrate his tool in our framework and enabled SAT result verification. ...
doi:10.1109/memcod.2011.5970515
dblp:conf/memocode/SlobodovaDSH11
fatcat:5vahhzcds5falllz5xqsvqraqq
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