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Implementing LDPC decoding on network-on-chip

T. Theocharides, G. Link, N. Vijaykrishnan, M.J. Irwin
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design  
In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip communication fabric that provides a 1.2Gbps decoded  ...  LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph.  ...  Network on Chip (NoC) Architecture The decoder is implemented as an on-chip network, where the bit and check nodes act as processing elements (PEs), which communicate via on-chip network routers, as shown  ... 
doi:10.1109/icvd.2005.109 dblp:conf/vlsid/TheocharidesLVI05 fatcat:zllutohveffqrecnzfp6kgs6ve

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

M.M. Mansour, N.R. Shanbhag, M.M. Mansour, N.R. Shanbhag
2006 IEEE Journal of Solid-State Circuits  
The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding  ...  The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations.  ...  Seok-Jun Lee for his assistance during the testing phase of the chip, and Dr. Makram M. Mansour for his support in building the parameterized leafcell layout library.  ... 
doi:10.1109/jssc.2005.864133 fatcat:osrslsl5zbeijmf24stbuibahm

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

T.L. Brandon, J.C. Koob, L. van den Berg, Zhengang Chen, A. Alimohammad, R. Swamy, J. Klaus, S. Bates, V.C. Gaudet, B.F. Cockburn, D.G. Elliott
2009 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process.  ...  On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.  ...  As well, a 78-Mb/s pipelined encoder was implemented on reconfigurable hardware [17] . We investigated the advantages of LDPC-CC encoders and decoders in previous implementations on FPGAs and ASICs.  ... 
doi:10.1109/tcsi.2009.2016592 fatcat:x7bzipwcijcr7b7vlgti5ywlte

A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications

Chih-Lung Chen, Yu-Cheng Lan, Hsie-Chia Chang, Chen-Yi Lee
2013 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)  
By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology.  ...  In this work, a decoder chip for time-invariant tailbiting LDPC convolutional code (TB-LDPC-CC) is proposed.  ...  ., ATU program (eNES), and National Chip Implementation Center for funding, chip fabrication and testing assistance.  ... 
doi:10.1109/asscc.2013.6691005 fatcat:q3fx6xclqzer5l6j55q47md2ye

Multi-Gb/s LDPC Code Design and Implementation

Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes.  ...  More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds.  ...  In our shift-LDPC decoder architecture, one block called CPU communication network is added to the CPUs to reduce the complexity of the shuffle networks.  ... 
doi:10.1109/tvlsi.2008.2002487 fatcat:otir74fmxbgtlkl5cveqvhu3sq

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes

Tyler Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott
2008 2008 IEEE International Symposium on Circuits and Systems  
A 600-Mb/s rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder was implemented in a 90-nm CMOS process. The encoder operates at 1.1 GHz and includes built-in all-phase termination.  ...  The size of the decoder controller is minimized by sharing it among an arbitrary number of decoder processors.  ...  We also thank the Canadian Microsystems Corporation for their VLSI design infrastructure and chip fabrication grants.  ... 
doi:10.1109/iscas.2008.4542111 dblp:conf/iscas/BrandonKBCASKBGCE08 fatcat:rbyqqrnlfnekdcwze45ny6sbg4

Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder

Hazem Moussa, Amer Baghdadi, Michel Jezequel
2008 2008 IEEE International Symposium on Circuits and Systems  
This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC/turbo decoder and based on the de Bruijn network.  ...  The flexibility and the scalability of this on-chip communication network enable it to be used in the emerging multi-code applications and standards.  ...  ON-CHIP COMMUNICATION NETWORK Figure 1.  ... 
doi:10.1109/iscas.2008.4541363 dblp:conf/iscas/MoussaBJ08 fatcat:iyj26aymargtznrhu4vopn5ugq

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 IEEE Journal of Solid-State Circuits  
An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented.  ...  With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without  ...  Chien-Ching Lin and Yen-Chin Liao for layout assistance and comments for paper writing, and the National Chip Implementation Center for chip measurement assistance.  ... 
doi:10.1109/jssc.2007.916610 fatcat:jxzk7hs2yfbsfhenqn7bebc7du

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications

Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2012 IEEE Journal of Solid-State Circuits  
After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s mm and energy efficiency of 62.4 pJ/b, respectively  ...  An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented.  ...  ACKNOWLEDGMENT The authors would like to thank National Chip Implement Center (CIC), Taiwan, and United Microelectronics Corporation (UMC), Taiwan, for technology support.  ... 
doi:10.1109/jssc.2012.2194176 fatcat:fpnbpkar2fcdbl4kgo3m7tergu

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
2015 ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)  
In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported.  ...  Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.  ...  In this work, we implement a 0.45nJ/bit, 1.31Gb/s with 96.6% chip utilization NB-LDPC decoder chip for small cell applications.  ... 
doi:10.1109/esscirc.2015.7313837 dblp:conf/esscirc/LeeYCCL15 fatcat:5uh45odwvjgyfnffosogdqhpve

A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications

Xin-Yu Shih, Cheng-Zhou Zhan, An-Yeu Wu
2008 2008 IEEE Asian Solid-State Circuits Conference  
This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system.  ...  The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS).  ...  Chip Implementation and Measurement Results For (1944, 972) LDPC codes in IEEE 802.11n system, the LDPC decoder chip is designed and fabricated via TSMC 0.13um VLSI technology.  ... 
doi:10.1109/asscc.2008.4708787 fatcat:df3awdndlzgijmaxsdedlyjjmu

A Reliability-Aware LDPC Code Decoding Algorithm

Matthias Alles, Torben Brack, Norbert Wehn
2007 2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring  
Hence increasing the robustness of chip implementations in terms of tolerating errors becomes mandatory. In this paper we present reliability-aware extensions of the LDPC decoding algorithm.  ...  We exploit application specific fault tolerance of the decoding algorithm combined with modifications on the algorithmic level to increase the reliability of a decoder implementation.  ...  LDPC DECODER IMPLEMENTATION The implementation of LDPC decoders is a challenging task. High throughput decoders require parallel or partly parallel architectures.  ... 
doi:10.1109/vetecs.2007.322 dblp:conf/vtc/AllesBW07 fatcat:q6nj5pvgpzanfjspomzvou5oaa

Hardwarearchitektur für einen universellen LDPC Decoder

C. Beuschel, H.-J. Pfleiderer
2009 Advances in Radio Science  
</strong> Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt.  ...  Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping  ...  decoder -Unconstrained code design -One hardware decoder for arbitrary LDPC codes -Hardware accelerator to find good codes -Multi-standard decoder Key Implementation Challenges for Fully Flexible  ... 
doi:10.5194/ars-7-213-2009 fatcat:aqjv7dqstvecdfw7doah4xzlly

Implementation of Data Encoding Techniques for Reducing Area, Power Consumption in Network-on-Chip for LDPC Applications

2016 International Journal of Science and Research (IJSR)  
As technology improves, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communicate ion subsystem, namely, the routers  ...  and the network interfaces (NIs).  ...  Hamming code is one of the examples of syndrome decoder. B. Majority Logic detector/decoder The ML detector/decoder (MLDD) has been implemented using the Euclidean Geometry LDPC.  ... 
doi:10.21275/v5i3.nov162344 fatcat:ksbfe5gmojd67bz4uomlaf45hm

A 1.1-Gb/s 4092-bit Low-Density Parity-Check Decoder

Engling Yeo, Borivoje Nikolic
2005 2005 IEEE Asian Solid-State Circuits Conference  
A 4092-bit low-density parity-check decoder, based on staggered decoding schedule, is implemented in a 130nm 6M CMOS technology. The rate 0.75 code is based on finitefield geometries.  ...  Serial, shift-register based architecture enables a compact decoder implementation.  ...  STMicroelectronics fabricated the test chip.  ... 
doi:10.1109/asscc.2005.251709 fatcat:czptndwpxzegzbmhh4rwvcgoou
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