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Immersion and dry lithography monitoring for flash memories (after develop inspection and photo cell monitor) using a darkfield imaging inspector with advanced binning technology

P. Parisi, A. Mani, C. Perry-Sullivan, J. Kopp, G. Simpson, M. Renis, M. Padovani, C. Severgnini, P. Piacentini, P. Piazza, A. Beccalli, Alek C. Chen (+3 others)
2009 Lithography Asia 2009  
This paper describes litho monitoring methodologies developed and implemented for flash devices for 65nm production and 45nm development using the darkfield imaging inspector.  ...  Capturing defects of interest (DOI) in the lithography cell rather than at later process steps shortens the cycle time and allows for wafer re-work, reducing overall cost and improving yield.  ...  The darkfield imaging inspector was implemented as a daily PM for the immersion lithography cell.  ... 
doi:10.1117/12.835839 fatcat:57dcumt6hfg3fplzivsbljtpzy

SpursEngine™ a high-performance stream processor derived from cell/B.E.™ for media processing acceleration

Hiroo Hayashi
2008 2008 IEEE Hot Chips 20 Symposium (HCS)  
, Toshiba Corporation SpursEngine™ Architecture Overview • Media processing accelerator derived from Cell Broadband Engine TM (Cell/B.E.  ...  PCIe eFuse PCIe PHY PLL SpursEngine TM Physical Implementation • Process: -65nm bulk CMOS with 7 levels of copper layers • Die Size: -9.98mm x 10.31mm, 102.89mm 2 • Fmax: 1.5GHz •  ...  face image. • It's easy to find highlight scenes from the 'clapping and cheers graph'. • Easily playback the movie from your desired scene by selecting a thumbnail.  ... 
doi:10.1109/hotchips.2008.7476534 fatcat:bmw2isbhvfh2bgnlmmq6jfzz54

Topics in integrated circuits for communications [Series Editorial]

Charles Chien, Zhiwei Xu, Stephen Molloy
2010 IEEE Communications Magazine  
The steep rise in available throughput has stimulated the growth of ubiquitous broadband services such as streaming of high-definition video contents, while on the other extreme, the steep drop in power  ...  The authors then demonstrate an example implementation and test chip for the architecture, capable of encoding a single view at a resolution of 4096 × 2160 or multiple views at lower resolution.  ... 
doi:10.1109/mcom.2010.5439079 fatcat:3lxbholjajfl7kptqbwsuofocm

A 0.5-to-3 GHz software-defined radio receiver using sample domain signal processing

Run Chen, Hossein Hashemi
2013 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
A 0.5-to-3 GHz software-defined radio receiver leveraging Sampled Domain Signal Processing (SPSD) is demonstrated in a 65nm LP CMOS technology.  ...  It achieves out-of-band IIP3 > 11.7 dBm, IIP2 > 58 dBm, NF = 5.5 ~ 8.8 dB, and uncalibrated 3 rd and 5 th order harmonic rejections exceeding 47 dB and 52 dB, respectively.  ...  ACKNOWLEDGEMENT This work was partially supported by the Office of Naval Research under the JCREW 3.3 Technologies program.  ... 
doi:10.1109/rfic.2013.6569592 fatcat:prjyl2gsk5ctvcfqklw5xdfixi

RFIC 2020 Program

2020 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
Two prototype N-path Shekel circulators have been implemented in 65nm CMOS.  ...  The FD receiver is implemented in a standard 65nm CMOS process and operates from 100MHz-1GHz with gain tunability of 15-38dB, noise figure of 5.4dB, and power consumption of 31mW.  ...  The Cartesian transmitter is implemented in a 65-nm CMOS process. The measured peak output power of the transmitter is 15.5 dBm with a 1.3 V supply.  ... 
doi:10.1109/rfic49505.2020.9218389 fatcat:fqkpw3oau5gzpoi3gscgb7kwhi

A 5–11 GHz 8-bit Precision Passive True-Time Delay in 65-nm CMOS Technology

Jeong-Moon Song, Jung-Dong Park
2022 IEEE Access  
The implemented 8-bit TTD circuit achieved a minimum delay of 1.56 ps and a maximum delay of 400 ps, demonstrating the smallest loss per delay among the recently reported state-of-the-art silicon-based  ...  To achieve a precision time delay control, the 8-bit TTD employs a 4-bit time delay circuitry that utilizes two LC delay networks in parallel to reduce the effects of the nonideal lumped components and  ...  ACKNOWLEDGMENT The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC).  ... 
doi:10.1109/access.2022.3150313 fatcat:sf5drvz2abdk5pnpwe4vkmehc4

Optimal design of aperiodic, vertical silicon nanowire structures for photovoltaics

Chenxi Lin, Michelle L. Povinelli
2011 Optics Express  
The spectral behavior mimics that of a periodic array with larger lattice constant. For our system, we find that randomlyselected, aperiodic structures invariably outperform the periodic array.  ...  The optimal structure is obtained using a random walk algorithm with transfer matrix method based electromagnetic forward solver.  ...  Acknowledgment The authors thank Dr. A. F. J. Levi for helpful discussions. Computing resources were provided by the USC Center for High Performance Computing and Communications.  ... 
doi:10.1364/oe.19.0a1148 pmid:21935258 fatcat:od73a3hce5hnhmaum5diebiemi

RF interconnects for communications on-chip

M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
broadband nature of RF-I.  ...  Layouts of a BPSK implementation of a 20GHz larger number of repeaters required to keep the same data rate.  ... 
doi:10.1145/1353629.1353649 dblp:conf/ispd/ChangSTCR08 fatcat:qrtu4uq7bjhe3nr36ouo47zqwq

Table of Contents

2021 2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA  
Sentiment Analysis MI-STA2021_paper ID# 106 Strategies towards the Implementation of Blended Learning in Engineering Education MI-STA2021_paper ID# 246 Popularity of Current Technology Trends in Arab  ...  and Tuning of PSS Using GA MI-STA2021_paper ID# 132 501 A Comprehensive Investigation into the Impact of Integrating High PV Penetration on The Libyan Network MI-STA2021_paper ID# 134 Effect of PV cells  ... 
doi:10.1109/mi-sta52233.2021.9464435 fatcat:2yfi7blqnnapjgfnqizn54ggma

Frank chang recognized for modern cell phone technology and WLAN systems

Mau-Chung Frank Chang
2006 IEEE Solid-State Circuits Society Newsletter  
He was responsible for the design of TI's first standard cell library.  ...  Paulraj is a Fellow of the IEEE and a Member of the Indian National Academy of Engineering.  ...  The conference begins with a short course on Sunday, October 8, followed by two full days of contributed and invited papers.  ... 
doi:10.1109/n-ssc.2006.6500129 fatcat:72ur4mgqvjeizf4tfsrudwgeaa

SiGe slips into main fabs

Mark Telford
2004 III-Vs review  
"The new chip design could be implemented within five years, enabling applications such as video streaming on cell phones," said Dr T C Chen, vice president of Science and Technology at IBM Research. had  ...  CMOS silicon's speed can be boosted by shrinking transistor dimension from 130nm to firstly 90nm then 65nm and 45nm, but only at great expense and difficulty, especially as the limits of CMOS scaling are  ... 
doi:10.1016/s0961-1290(04)00281-9 fatcat:eb6zz4rldnhmvgup2b5tzfguiy

Program

2020 2020 IEEE/MTT-S International Microwave Symposium (IMS)  
He was the FOX-1 project systems engineer and was elected AMSAT V.P. of engineering in April 2014.  ...  Jerry was a driving force behind securing funding and implementation of the GOLF 3U Cubesat program which includes the GOLF-TEE and GOLF-1.  ... 
doi:10.1109/ims30576.2020.9223840 fatcat:bx4dclbhwnfv3in7m6h2it7r3u

A Wide-angle, Enhanced Oblique Incidence, Bend-able Metamaterial Absorber Employed in Visible Region with a Sun Shape Resonator

Md Mizan Kabir Shuvo, Md Imran Hossain, Sydur Rahman, Sultan Mahmud, Sikder Sunbeam Islam, Mohammad Tariqul Islam
2021 IEEE Access  
The dielectric spacer thickness "ts" is swept for the values of 45 to 65nm with an increment of 5nm and the corresponding results are illustrated in Fig. 6(b) .  ...  So, the set of values of the geometrical parameters in which the proposed structure is designed gives proper absorbance and this set of values must be ensured for practically implementing the proposed  ... 
doi:10.1109/access.2021.3111813 fatcat:rpqrmozj3nhordnct6pwycruzu

An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem

Turbo Majumder, Souradip Sarkar, Partha Pande, Ananth Kalyanaraman
2010 ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors  
In this paper, we present the design and implementation of the processing elements with a highly optimized lower bound computation kernel and evaluate its performance.  ...  We adopted this approach in an NoC-based implementation for solving TSP targeted towards phylogenetics taking advantage of the fine-grained parallelism and efficient communication network.  ...  On hardware acceleration targeted towards phylogenetics applications, substantial work has been carried out based on platforms like FPGA, Graphics Processing Unit (GPU), Cell Broadband Engine (CBE) and  ... 
doi:10.1109/asap.2010.5540797 dblp:conf/asap/MajumderSPK10 fatcat:4hupknipozgq5h72uecz3lglkm

Detailed Author Index

2020 2020 IEEE/MTT-S International Microwave Symposium (IMS)  
A 623 C A 300GHz Wireless Transceiver in 65nm CMOS for IEEE802.15.3d Using Push-Push Subharmonic Mixer (We2C-1) A 532 C Non-Reciprocal Lithium Niobate-on-Silicon Acoustoelectric Delay Lines (We1E-5)  ...  and Stacked PA Cells Across 50-70GHz and 64-110GHz in 250nm InP (Tu4F-2) 1295 C Transformer-Based Broadband mm-Wave InP PA Across 42-62GHz with Enhanced Linearity and Second Harmonic Engineering (Th3E  ...  (Tu3H-1) 405 C Broadband PA Architectures with Asymmetrical Combining and Stacked PA Cells Across 50-70GHz and 64-110GHz in 250nm InP (Tu4F-2) Transformer-Based Broadband mm-Wave InP PA Across 42-62GHz  ... 
doi:10.1109/ims30576.2020.9223810 fatcat:4pzggneub5c5ddwi4gmbotr6gy
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