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An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS

Hongying Wang, Filippo Schembari, Marek Miskowicz, Robert Bogdan Staszewski
2019 IEEE Solid-State Circuits Letters  
The AR quasi-LCS ADC is implemented as a delta-modulator and adopts a 4-bit asynchronous SAR ADC to quantize the residue voltage signal, thus allowing a straightforward implementation of LCS and AR algorithms  ...  Fabricated in 28-nm CMOS, this ADC achieves an SNDR of 53 dB over 1.42 MHz signal bandwidth while consuming 205 µW and an active area of 0.0126 mm 2 .  ...  The 4-bit residue quantizer is implemented as a top-plate sampling asynchronous SAR ADC with split binary-weighted capacitive DAC (apart from the LSB capacitors C 0 , which are not split).  ... 
doi:10.1109/lssc.2019.2899723 fatcat:wthg5fhycjb5hgoab46mg52ch4

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Jianwen Li, Xuan Guo, Jian Luan, Danyu Wu, Lei Zhou, Nanxun Wu, Yinkun Huang, Hanbo Jia, Xuqiang Zheng, Jin Wu, Xinyu Liu
2020 Electronics  
By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode  ...  The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.  ...  An adaptive power/ground [23] is adopted to compensate the common-mode voltage mismatch between the blocks at 1.8 V power supply and the SAR quantizer.  ... 
doi:10.3390/electronics9020375 fatcat:27yugmsyazbpbjhic2ewaqhcdy

A 0.8 V asynchronous ADC for energy constrained sensing applications

M. Trakimas, S. Sonkusale
2008 2008 IEEE Custom Integrated Circuits Conference  
The idea of using an adaptive resolution to increase the maximum input frequency of the ADC is introduced. A prototype chip has been fabricated in a 0.18 µm CMOS process.  ...  This paper discusses the design of an asynchronous analog-to-digital converter targeted for low-power sensing applications.  ...  The designed ADC allows for an adaptive resolution control algorithm to be implemented in the future. This will increase the maximum input frequency that the ADC can process.  ... 
doi:10.1109/cicc.2008.4672051 dblp:conf/cicc/TrakimasS08 fatcat:f5piqr47rvaz5htme53qbebhju

Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion

Brandon M. Kelly, Alexander T. DiLello, David W. Graham
2019 Journal of Low Power Electronics and Applications  
The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications  ...  This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter.  ...  Conflicts of Interest: The funding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; and in the decision to publish  ... 
doi:10.3390/jlpea9030025 fatcat:rd4vqlmwcjacdo35lh3ut7jm6q

An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization

Hongying Wang, Filippo Schembari, Robert Bogdan Staszewski
2019 IEEE Journal of Solid-State Circuits  
The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive-approximation-register (SAR) sub-ADC, which enables a straightforward implementation of  ...  Index Terms-Adaptive resolution (AR), analog-to-digital converter (ADC), asynchronous successive-approximation-register (SAR) ADC, compressed sensing, event-based signal processing, Internet of Things  ...  The residue quantizer is implemented as a 4-bit asynchronous top-plate-sampling SAR sub-ADC ("4b sub-ADC").  ... 
doi:10.1109/jssc.2019.2950175 fatcat:ow7bc6eo3ndxnasenj5ljsqadi

Architectural Advancement of Digital Low-Dropout Regulators

Muhammad Abrar Akram, In-Chul Hwang, Sohmyung Ha
2020 IEEE Access  
In addition, some asynchronous DLDOs do not require C OU T thanks to their parallel implementation with a switching-mode DC-DC converter [29] , [42] , [58] .  ...  It recovers an undershoot of 45 mV within 25 ns for a step load current of 200 mA with peak current efficiency of 99.96%.  ...  In addition, he was also involved in the development of adaptive and distributed PMU based on unified voltage and frequency regulators.  ... 
doi:10.1109/access.2020.3012467 fatcat:qpkm4ix7nbaopfwr4zr3nmx2a4

A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping

Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012 2012 IEEE International Symposium on Circuits and Systems  
In a standard 65nm CMOS process, an SNDR of 51 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 65 MHz, where the power is 271 μW. I.  ...  Because no switched capacitor or opamp is used, the proposed TDC can be implemented in a small area and with low power. Mismatches in the oscillation frequency between the DCOs might occur.  ...  ACKNOWLEDGMENTS This development was performed by the author for STARC as part of the Japanese Ministry of Economy, Trade and Industry sponsored "Silicon Implementation Support Program for Next Generation  ... 
doi:10.1109/iscas.2012.6271996 dblp:conf/iscas/KonishiOIYK12 fatcat:ghcpqk26jvba5kfnvldi3djfg4

A Level-Crossing Based QRS-Detection Algorithm for Wearable ECG Sensors

Nassim Ravanshad, Hamidreza Rezaee-Dehsorkh, Reza Lotfi, Yong Lian
2014 IEEE journal of biomedical and health informatics  
Simulated with MIT-BIH Arrhythmia Database, the proposed system delivers an average detection accuracy of 98.3%, a sensitivity of 98.89%, and a positive prediction of 99.4%.  ...  In this paper, an asynchronous analog-to-information conversion system is introduced for measuring the RR intervals of the electrocardiogram (ECG) signals.  ...  The level-crossing sampling, on the other hand, is an irregular or asynchronous sampling method.  ... 
doi:10.1109/jbhi.2013.2274809 pmid:24403416 fatcat:4grui2bclvcyxi6yxptgx57sjm

An AC-Coupled Wideband Neural Recording Front-End With Sub-1mm2×fJ/conv-step Efficiency and 0.97 NEF

Arda Uran, Yusuf Leblebici, Azita Emami, Volkan Cevher
2020 IEEE Solid-State Circuits Letters  
The proposed unit conditions local field and action potentials using an inverter-based capacitively-coupled low-noise amplifier, followed by a perchannel 10-bit asynchronous SAR ADC.  ...  The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated.  ...  Kerim Ture for their help with the test setup, and Carlotta Gastaldi for taking the micrograph.  ... 
doi:10.1109/lssc.2020.3013993 fatcat:tbir7yz73bbqpb5ynnwtkmomfa

Design of a Linear Voltage to Frequency Converter for Digital Audio Applications

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
With the proposed VFC and ADC, the interface produced a good SNR compared to the conventional audio interfaces.  ...  The design is implemented in PSoC and the performance is analysed with the previous technologies. Parameters such as sensitivity, output frequency and power consumption are analysed.  ...  The behaviour of this design is appropriate with various applications, because the transfer of synchronous data is always smoother to deal with compared to the asynchronous mode.  ... 
doi:10.35940/ijitee.a5321.119119 fatcat:x2wmkdnatvc3ldelwseejxb7qu

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

Anita Arvind Deshmukh, Raghvendra B. Deshmukh
2016 EURASIP Journal on Advances in Signal Processing  
This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power.  ...  Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power.  ...  Acknowledgements The work is carried out under SMDP II supported by MCIT, Government of India. Project is reviewed frequently by Dr. W. S. Khokle and Dr. R. M. Patrikar.  ... 
doi:10.1186/s13634-016-0399-y fatcat:wfavwqeplrendncckaew5jrhqy

Low-Power Area-Efficient Decimation Filters in Sigma-Delta ADCs

Feng Yi, Xiaobo Wu, Jian Xu
2007 2007 IEEE Conference on Electron Devices and Solid-State Circuits  
The SAR features a dynamic comparator so that the quantizer power automatically scales with the different clock frequencies, and operates with asynchronous logic so that it does not need an additional  ...  A common method to achieve a scalable analogue power is to adaptively scale transistor bias currents with the sampling rate [12] - [13] .  ... 
doi:10.1109/edssc.2007.4450255 fatcat:uciajdoalrdqnd2gy2ntdhwkoa

Table of contents

2017 2017 IEEE International Symposium on Circuits and Systems (ISCAS)  
Base Recombination Current U-85 -urrent Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced ReliabilityU-86 -Power Efficient SAR ADC Adaptive to Input Activity for ECG Monitoring ApplicationsU  ...  Reduction by an Adaptive CTIA Photocircuit for Room Temperature SWIR SensingO-24 -A Battery-Less, 255 Na Quiescent Current Temperature Sensor with Voltage Regulator Fully Powered by Harvesting Ambient  ... 
doi:10.1109/iscas.2017.8049750 fatcat:csazlovzq5g4bmzlf7uss65sy4

A Digital Pixel Sensor Array With Programmable Dynamic Range

A. Kitchen, A. Bermak, A. Bouzerdoum
2005 IEEE Transactions on Electron Devices  
Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 A per DPS.  ...  The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range.  ...  We have proposed a novel pixel architecture based on an asynchronous self-resetting mode, which has the advantage, over the synchronous self-resetting mode, of avoiding large peak by using a start integration  ... 
doi:10.1109/ted.2005.859698 fatcat:cngx5tfz45gs3jwfs45ninbjsm

A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations

Ju Eon Kim, Taegeun Yoo, Dong-Kyu Jung, Dong-Hyun Yoon, Kiho Seong, Tony Tae-Hyoung Kim, Kwang-Hyun Baek
2020 IEEE Access  
The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption.  ...  INDEX TERMS Asynchronous, compensation, low power, process voltage temperature (PVT), successive approximation register (SAR) analog-to-digital converter (ADC).  ...  FIGURE 8 . 8 The schematic of an adaptive boosting comparator (ABC). FIGURE 9 . 9 Schematic of C-DAC with resolution reconfigurable function. FIGURE 10 . 10 Fabricated die micrograph.  ... 
doi:10.1109/access.2020.2998161 fatcat:3hftlmvhzzbwfhnhxyfzxs7r54
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