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Implementation of a simplified network processor

Qiang Wu, Danai Chasaki, Tilman Wolf
2010 2010 International Conference on High Performance Switching and Routing  
For packet forwarding, our simplified network processor can achieve a throughput of 2.79 Gigabits per second at a clock rate of only 62.5 MHz.  ...  Based on our initial system design, we present a prototype implementation of a 4-core network processor using the NetFPGA platform.  ...  In this paper, we present a prototype implementation of our simplified network processor.  ... 
doi:10.1109/hpsr.2010.5580273 dblp:conf/hpsr/WuCW10 fatcat:5p6czfcbizgehm4iusyuq63he4

The Case for RISP: A Reduced Instruction Spiking Processor [article]

James S. Plank, ChaoHui Zheng, Bryson Gullett, Nicholas Skuda, Charles Rizzo, Catherine D. Schuman, Garrett S. Rose
2022 arXiv   pre-print
In this paper, we introduce RISP, a reduced instruction spiking processor.  ...  While most spiking neuroprocessors are based on the brain, or notions from the brain, we present the case for a spiking processor that simplifies rather than complicates.  ...  One of our current research projects is to implement these and similar observations to simplify RISP networks.  ... 
arXiv:2206.14016v1 fatcat:d54voadr3baebemuhi3ksnhpzm

Design of a network service processing platform for data path customization

Qiang Wu, Tilman Wolf
2009 Proceedings of the 2nd ACM SIGCOMM workshop on Programmable routers for extensible services of tomorrow - PRESTO '09  
We present a novel hardware architecture for high-performance processing of such network services in the data path.  ...  The design provides simple processing units to implement services and a custom hardware infrastructure to manage packets and processing context.  ...  The packet processing systems of programmable routers are typically implemented using network processors [21, 25] , with a number of commercial network processors being available from Intel, AMCC, EZchip  ... 
doi:10.1145/1592631.1592639 dblp:conf/sigcomm/WuW09 fatcat:idnp2p6725d6xfzdz2kybljcsi

Video and USB Transmission Devices for Cloud Desktop Service [chapter]

Chanho Park, Hagyoung Kim
2016 Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering  
In the hardware device, a simplified switch is adopted to support multi-user.  ...  To solve this problem, a passthrough virtualization system which assigns a graphic card to each user is used and hardware devices which transfer video and USB signals to the network are developed.  ...  Therefore, the simplified form of switch can be used instead of a general switch chip. Figure 3 shows a simplified model of a switch chip.  ... 
doi:10.1007/978-3-319-38904-2_19 fatcat:g23l3sbkdndhxgfogbim62vqym

A multiprocessor architecture for the massively parallel model GCA

W. Heenes, R. Hoffmann, J. Jendrsczok
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
The architecture mainly consists of a number of cell processors and a network. The cell processors are dedicated RISC processors, the network is a crossbar implemented with multiplexers.  ...  Only read-accesses through the network are necessary in the GCA model leading to a simplified structure. A system with 32 processors was implemented as a prototype on a FPGA.  ...  As in the GCA model a cell is not allowed to modify the contents of another cell, the network design is simplified because write accesses need not to be implemented.  ... 
doi:10.1109/ipdps.2006.1639700 dblp:conf/ipps/HeenesHJ06 fatcat:vzrqvle6qnhfjhvh7p2lb3lnmy

Migrating objects in electronic commerce applications [chapter]

Marko Boger
1998 Lecture Notes in Computer Science  
This paper presents a distributed extension to Java named Dejay. Its aim is to simplify the design and development of such distributed systems.  ...  They contain groups of objects and manage their synchronization and migration over distributed networks. It is used as an implementation language for distributed electronic commerce applications.  ...  It can be implemented by either of these and the objects that are executing within a virtual processor should not be aware of the form of implementation used.  ... 
doi:10.1007/bfb0053414 fatcat:srt3qya2ijfb5el3vdv52tzcsq

Simplifying data path processing in next-generation routers

Qiang Wu, Danai Chasaki, Tilman Wolf
2009 Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '09  
In our work, we propose a new packet processor design that simplifies packet processing by managing packet contexts in hardware. We show how such a design scales to large systems.  ...  Customizable packet processing is an important aspect of next-generation networks. Packet processing architectures using multi-core systems on a chip can be difficult to program.  ...  Programmable packet processing engines can be implemented using several different technologies ranging from general-purpose workstations processors [3] to embedded multicore systems-on-a-chip network  ... 
doi:10.1145/1882486.1882492 dblp:conf/ancs/WuCW09 fatcat:fvwnttujjfh47f7q3nnjedg4em

Exploring FPGA network on chip implementations across various application and network loads

Graham Schelle, Dirk Grunwald
2008 2008 International Conference on Field Programmable Logic and Applications  
Naively it would be assumed that these complex network on chip architectures would perform better than simplified implementations.  ...  Current mainstream FPGA parts only support very small network on chip topologies, due to the high resource utilization of virtual channel based implementations.  ...  The Simple NoC Implementation With those 3 components that create a basic network on chip, each component can be simplified in order to create the simplest network on chip implementation.  ... 
doi:10.1109/fpl.2008.4629905 dblp:conf/fpl/SchelleG08 fatcat:lbaksbxffzbqlmrd2dajh7dq4u

Considering processing cost in network simulations

Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
2003 Proceedings of the ACM SIGCOMM workshop on Models, methods and tools for reproducible network research - MoMeTools '03  
In many network simulations and models the cost of processing a packet is considered negligible or overly simplified.  ...  NPEST can be programmed in C and greatly simplifies the implementation and simulation process as compared to using network processor simulators.  ...  generates (which is implemented in hardware on a real router or network processor and thus is not a processing cost per se).  ... 
doi:10.1145/944781.944782 fatcat:hwlnvhrfzvcindk3vgzrascsjm

Considering processing cost in network simulations

Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
2003 Proceedings of the ACM SIGCOMM workshop on Models, methods and tools for reproducible network research - MoMeTools '03  
In many network simulations and models the cost of processing a packet is considered negligible or overly simplified.  ...  NPEST can be programmed in C and greatly simplifies the implementation and simulation process as compared to using network processor simulators.  ...  generates (which is implemented in hardware on a real router or network processor and thus is not a processing cost per se).  ... 
doi:10.1145/944773.944782 fatcat:xnheqezatnei3gwh4v6ol7d4rq

A Methodology for Generating Application-Specific Heterogeneous Processor Arrays

S. Craven, C. Patterson, P. Athanas
2006 Proceedings of the 39th Annual Hawaii International Conference on System Sciences (HICSS'06)  
By individually optimizing each processor for its specific program the performance of the array is increased, while the common basic interface between processors eases optimization, implementation, debugging  ...  To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point  ...  The benefits of a simple processor interconnect network have been recognized.  ... 
doi:10.1109/hicss.2006.15 dblp:conf/hicss/CravenPA06 fatcat:osez6ixamvcwtmpv3rvms7bymi

ClusterNet: An Object-Oriented Cluster Network [chapter]

Raymond R. Hoare
2000 Lecture Notes in Computer Science  
Consequently, functions that involve data from a group of processors must be implemented on top of message routing.  ...  We propose treating the network switch as a function unit that can receive data from a group of processors, execute operations, and return the result(s) to the appropriate processors.  ...  Rather than accepting this overhead, we propose expanding the functionality of the network and simplifying the network interface.  ... 
doi:10.1007/3-540-45591-4_4 fatcat:ntvt4tfhvbavxkirqtcvohor3q

Multicast snooping

E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood
1999 SIGARCH Computer Architecture News  
Processors handle transactions as they would with a snooping protocol, while a simplified directory operates in parallel to check masks and gracefully handle incorrect ones (e.g., previous owner missing  ...  Preliminary performance numbers with mostly SPLASH-2 benchmarks running on 32 processors show that we can limit multicasts to an average of 2-6 destinations (<< 32) and we can deliver 2-5 multicasts per  ...  A simplified directory in memory checks the mask of each transaction, detecting masks that omit necessary processors and taking corrective action.  ... 
doi:10.1145/307338.301004 fatcat:tjmdntmn4zafjhxyp5652bpmw4

Strategy-Accurate Parallel Buchberger Algorithms

GIUSEPPE ATTARDI, CARLO TRAVERSO
1996 Journal of symbolic computation  
We provide a detailed analysis the maximum potential degree of parallelism that is achievable with such architecture.  ...  The analysis corresponds to the results of our experimental implementation and also explains similar results obtained by other authors.  ...  Acknowledgements The International Computer Science Institute in Berkeley provided access to its network of workstations to carry out our experiments.  ... 
doi:10.1006/jsco.1996.0022 fatcat:pcbcadkxkngbzjin7e5mkwopo4

NP-Click: a productive software development approach for network processors

Niraj Shah, W. Plishker, Kaushik Ravindran, K. Keutzer
2004 IEEE Micro  
to implement on a network processor.  ...  and a variety of on-chip communication mechanisms. 1 This focus on architecture design for network processors has made programming them an arduous task.  ...  Applicability to additional network processors This research implemented NP-Click on the Intel IXP1200, a popular network processor.  ... 
doi:10.1109/mm.2004.53 fatcat:j3pp2sj3urah3fw34ghocqe6gq
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