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Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
the read and write stability of an SRAM cell.  ...  In this work, we carried out Monte Carlo based SNM simulations to study the impact of gate length and fin width on the cell read stability for all schemes.  ...  Watson Research Center, Yorktown Heights, NY, working on scaled bipolar devices, technology, and circuits.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

Digital and analog TFET circuits: Design and benchmark

S. Strangio, F. Settino, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi
2018 Solid-State Electronics  
cell in [36]), in many cases employing transistors that are not at the state-of-the-art of TFETs and are based on silicon platforms.  ...  The performance of track and hold and comparators based on complementary heterojunction TFETs has been assessed in [9].  ...  FinFETs have fin height hfin=21 nm, fin width tfin=8 nm, LG=14 nm and EOT= 0.88 nm (physical oxide thickness of 1.2 nm [60] ).  ... 
doi:10.1016/j.sse.2018.05.003 fatcat:ptppcp6mancw7glfdwpvaiyoem

2020 Index IEEE Transactions on Electron Devices Vol. 67

2020 IEEE Transactions on Electron Devices  
of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs; TED Jan. 2020 4-10 Gupta, C., Gupta, A., Vega, R.A., Hook, T.B., and Dixit, A., Impact of Hot-Carrier Degradation on Drain-Induced  ...  Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating; TED May 2020 2208-2212 Gupta, M., see Kumar, P., TED Nov. 2020 5221-5228 Gupta, M., see Siddharth, G., TED Dec. 2020 5587-5592  ...  ., +, TED Dec. 2020 5408-5414 Strong Read and Write Interference Induced by Breakdown Failure in Crossbar Arrays.  ... 
doi:10.1109/ted.2021.3054448 fatcat:r4ertn5jordkfjjvorvss7n6ju

State of the Art and Future Perspectives in Advanced CMOS Technology

Henry H. Radamson, Huilong Zhu, Zhenhua Wu, Xiaobin He, Hongxiao Lin, Jinbiao Liu, Jinjuan Xiang, Zhenzhen Kong, Wenjuan Xiong, Junjie Li, Hushan Cui, Jianfeng Gao (+8 others)
2020 Nanomaterials  
Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according  ...  This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology.  ...  Figure 43 . 43 Simulated read static noise margin (SNM) vs. write noise margin (WNM) of the Static Random Acess Memory (SRAM) cell considering HCI degradation and HCI together with BTI degradation after  ... 
doi:10.3390/nano10081555 pmid:32784801 pmcid:PMC7466708 fatcat:yssyxekom5hslivtbxbphjg6h4

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS [article]

Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz
2014 arXiv   pre-print
Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress.  ...  We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template.  ...  Acknowledgements This work was supported by the Center for Hierarchical Manufacturing (CHM, NSF DMI-0531171), and NSF (CCF-0508382) grants.  ... 
arXiv:1404.0607v1 fatcat:do4ib2js3bamrk36534pfoiu3q

2021 Index IEEE Transactions on Electron Devices Vol. 68

2021 IEEE Transactions on Electron Devices  
-that appeared in this periodical during 2021, and items from previous years that were commented upon or corrected in 2021.  ...  The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TED Nov. 2021 5346-5349 Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs.  ... 
doi:10.1109/ted.2021.3138305 fatcat:37sowz27xjc4bjhktlrldi2nja


Avinash Yadav
In the era of high-speed circuits and systems, CMOS technology has reached its limits. The balance of power, performance, and area trade-off is the base of current digital systems.  ...  An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device.  ...  The write "1" operation is not possible by forcing Q through the access transistor M7 on the account of the read stability.  ... 
doi:10.25394/pgs.13335494.v1 fatcat:4zmkhntx3vbwnpjakdjws4kys4

Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits

Serge Ecoffey
Of course my first thought goes to Prof. Adrian Ionescu, who gave me the opportunity and the privilege to realize my PhD in his laboratory.  ...  I came to the electronics laboratory with a material science background and Didier had the tough task, and enormous patience, to teach me quite everything about silicon technology and the work in the clean  ...  English Very good in reading, writing and speaking. German Good in reading, writing and speaking with limited vocabulary. Italian Very good in reading and speaking, more difficulties in writing.  ... 
doi:10.5075/epfl-thesis-3722 fatcat:hqyihx5rubabxpudmenmitjo34

Designing, Implementing, and Testing Hardware for Cybersecurity

J Brown
This thesis is focussed on the most promising new developments in the hardware aspect of this battle for security.  ...  Cybersecurity is one of the key issues facing the world today.  ...  [121] reduce RTN amplitude by changing the fin height direction in FinFET transistors, we could follow the same process but with the opposite goal of increasing RTN impact by varying the fin height  ... 
doi:10.24377/ljmu.t.00014649 fatcat:af4bd4gcpjgwtbvyvhgcohyyuy