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Impact of technology scaling on metastability performance of CMOS synchronizing latches

M.S. Baghini, M.P. Desai
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design  
In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers.  ...  We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay.  ...  (a) Conventional cell CMOS D-latch (b) Synchronously setasynchronously reset flip-flop To survey the impact of technology scaling on the metastability performance of the two latches considered in above  ... 
doi:10.1109/aspdac.2002.994941 dblp:conf/vlsid/BaghiniD02 fatcat:zicexonoanbfdmcgog6f2smfr4

A new 65nm LP metastability measurment test circuit

Salomon Beer, R. Ginosar
2012 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel  
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond.  ...  A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown  ...  Evidently, as technology scales, and increase and to maintain high MTBF must decrease as well. In the past, was believed to improve with technology scaling [4] .  ... 
doi:10.1109/eeei.2012.6377044 fatcat:4c2o7nncq5f3zochivncsfti4m

Metastability Challenges for 65nm and Beyond; Simulation and Measurements

Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and below.  ...  A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system is shown that accounts for changes in delay values due to  ...  Evidently, as technology scales, and increase and to maintain high MTBF must decrease as well. In the past, was believed to improve with technology scaling [4] .  ... 
doi:10.7873/date.2013.268 dblp:conf/date/BeerGCCZ13 fatcat:xgvwmjcbfrhghl6idspe35u37m

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs

Doris Chen, Deshanand Singh, Jeffrey Chromczak, David Lewis, Ryan Fung, David Neto, Vaughn Betz
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
The impact of metastability is increasing as process geometries shrink and supply voltages drop faster than transistor Vts.  ...  Through our detailed experimental results, we show that we can improve the metastability characteristics of a large suite of industrial benchmarks by an average of 268,000 times with our optimization techniques  ...  no impact on system latency, and with minimal impact on design operating speed.  ... 
doi:10.1145/1723112.1723142 dblp:conf/fpga/ChenSCLFNB10 fatcat:3lw2qtjd6fahzdd3nlnbia2voi

Stacked strained silicon transistors for low-power high-performance circuit applications

H. Ramakrishnan, S. Shedabale, G. Russell, A. Yakovlev
2008 2008 58th Electronic Components and Technology Conference  
These tools permitted the identification and modelling of those process parameters whose variation would have the greatest impact on circuit performance.  ...  As devices dimensions are scaled down, process variations can have a dramatic effect on the overall circuit performance.  ...  Variability Analysis: Jamb Latch Synchronizer In this section we explore the possibility of performance enhancement in terms of metastability resolution time in synchronizers using strained-Si transistors  ... 
doi:10.1109/ectc.2008.4550224 fatcat:ijp5zrokxbebrlv5w2b7ua2c44

Multithreshold MOS Current Mode Logic Based Asynchronous Pipeline Circuits

Kirti Gupta, Neeta Pandey, Maneesha Gupta
2012 ISRN Electronics  
The proposed circuits are implemented and simulated in PSPICE using TSMC 0.18 μm CMOS technology parameters. The performance of the proposed circuits is compared with the conventional MCML circuits.  ...  The results indicate that the proposed circuits reduce the power consumption by 21 percent in comparison to the conventional ones.  ...  The synchronous circuits suffer from the problems of clock distribution and clock skew which becomes a challenge to overcome as the technology scales down.  ... 
doi:10.5402/2012/529194 fatcat:plkkluhezfhxdo4cwjcpguhvoy

High Rate Data Synchronization in GALS SoCs

R. Dobkin, R. Ginosar, C.P. Sotiriou
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The risk of metastability in the synchronizer is analyzed in a technology-independent manner.  ...  A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described.  ...  We also present a technology-independent analysis of the metastability risk in the synchronizer, and its effect on the synchronizer architecture. Fig. 1 . 1 GALS system [9] .  ... 
doi:10.1109/tvlsi.2006.884148 fatcat:7gna2i7pmjdajfxkdeu6xrdc2y

Using FPGAs to implement self-timed systems

Erik Brunvand
1993 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications  ...  In order to ease the complexity of this style of design, however, suitable self-timed circuit primitives must be available to the system designer.  ...  Acknowledgments Many thanks to the students in my CS572 VLSI Architecture class for helping to work the bugs out of this library, and to Nick Michell for additional testing and the design of the carry  ... 
doi:10.1007/bf01607880 fatcat:ymmrqmc63vbelok42b4pi4gfim

Substrate coupling in digital circuits in mixed-signal smart-power systems

R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T.E. Watrobski, C. Morton, W. Staub, T. Tellier, I.S. Kourtev, E.G. Friedman
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems.  ...  The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit.  ...  For CMOS circuits, latch-up and metastability are shown to be the primary mechanisms affecting the integrity of a digital output.  ... 
doi:10.1109/tvlsi.2003.820526 fatcat:gkotss72ibborgwo7k7aiwultu

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel
2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library  ...  Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design.  ...  This work is supported in part by a grant received from the Ministry of Electronics and Information Technology (MEITY), Government of India for a Special Manpower Development Project for Chips to System  ... 
doi:10.1109/tcsi.2020.2965073 fatcat:lfxfwcahpvd37ezsn5jcequu2e

Chain: a delay-insensitive chip area interconnect

J. Bainbridge, S. Furber
2002 IEEE Micro  
This corresponds to 120 Mbps per wire on 0.35micron CMOS technology and 160 Mbps per wire on 0.18-micron CMOS technology.  ...  Parameterizable performance Although individual Chain links deliver significant throughput, many systems require greater than the 700 Mbps available over a single link (on 0.35-micron CMOS technology).  ...  It is now possible to construct large-scale SOCs without encountering the problems of synchronous interconnects.  ... 
doi:10.1109/mm.2002.1044296 fatcat:uo4ixfztp5fxrbg24bblkv2voy

Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS

Popong Effendrik, Wenlong Jiang, Marcel van de Gevel, Frank Verwaal, R. Bogdan Staszewski
2011 2011 20th European Conference on Circuit Theory and Design (ECCTD)  
One of them is the time-to-digital converter (TDC) system. A TDC in state-of-the-art 40 nm CMOS technology for WiMAX ADPLL system is chosen and presented in this thesis.  ...  To anticipate the future demands on WiMAX technology, we proposed an ADPLL (all-digital phase locked loop) solution for the WiMAX system.  ...  voltage and temperature have a global impact on the performance of the TDC.  ... 
doi:10.1109/ecctd.2011.6043362 dblp:conf/ecctd/EffendrikJGVS11 fatcat:xl6owkqqtbc3hbf5sszmvxafci

Low Power and Energy Efficient Asynchronous Design

Peter A. Beerel, Marly E. Roncken
2007 Journal of Low Power Electronics  
Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains  ...  including microprocessors, application specific designs, and networks on chip.  ...  We also thank Ivan Sutherland for helping us use the terms "energy" and "power" consistently, and for accepting-to his regret-our use of "open" and "closed" for latches.  ... 
doi:10.1166/jolpe.2007.138 fatcat:erlvur724ngp7bzbuluf2yn3se

Narrowing the margins with elastic clocks

Jordi Cortadella, Luciano Lavagno, Djavad Amiri, Jonas Casanova, Carlos Macian, Ferran Martorell, Juan A. Moya, Luca Necchi, Danil Sokolov, Emre Tuncer
2010 2010 IEEE International Conference on Integrated Circuit Design and Technology  
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance.  ...  Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic  ...  The impact of these cycles on the performance requires an analysis similar to that for synchronous systems with useful skew. The constraint of "working in unison" can also be relaxed.  ... 
doi:10.1109/icicdt.2010.5510273 fatcat:4euypvwomverfls56mmhyhcmym

A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

Anh T. Tran, Dean N. Truong, Bevan M. Baas
2009 2009 IEEE International Symposium on Circuits and Systems  
of one word per cycle.  ...  The globally asynchronous locally synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing global clocking circuits at high clock frequencies  ...  INTRODUCTION In deep submicron CMOS, the parasitic effects of wire interconnects-resistive, capacitive, and inductive-on system performance are no longer negligible.  ... 
doi:10.1109/iscas.2009.5117926 dblp:conf/iscas/TranTB09 fatcat:n3lmwjumw5cy3c7hrvshqcfhg4
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