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Impact of FPGA architecture on resource sharing in high-level synthesis

Stefan Hadjis, Andrew Canis, Jason H. Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz Czajkowski
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used.  ...  Resource sharing is a key area-reduction approach in highlevel synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the highlevel circuit specification  ...  In this paper, we examine the impact of the FPGA logic element architecture on the effectiveness of resource sharing.  ... 
doi:10.1145/2145694.2145712 dblp:conf/fpga/HadjisCACNBC12 fatcat:rtplkypqqvatdcpgx7ke45mpym

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Juanjo Noguera, Stephen Neuendorffer, Sven Van Haastregt, Jesus Barba, Kees Vissers, Chris Dick
2011 Analog Integrated Circuits and Signal Processing  
In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools.  ...  the low-level FPGA implementation details.  ...  High-level synthesis for FPGA High-level synthesis tools take as their input a high-level description of the specific algorithm to implement and generate the RTL description of FPGA implementation.  ... 
doi:10.1007/s10470-011-9765-8 fatcat:j5t7ikalxrcozjwqqkhsuiffne

Efficient DSP algorithm development for FPGA and ASIC technologies

Shiv Balakrishnan, Chris Eddington
2007 2007 IFIP International Conference on Very Large Scale Integration  
The use of Digital Signal Processing (DSP) in electronic products is increasing at a phenomenal rate.  ...  This paper discusses the challenges and requirements of creating portable algorithmic IP for FPGAs and ASICs and illustrates how an ESL synthesis methodology using the Synplify ® DSP tool can significantly  ...  Synplicity's DSP synthesis concept is based on four key elements: • Use of Electronic System Level (ESL) models with high levels of architectural and hardware abstraction • Automatic optimizations based  ... 
doi:10.1109/vlsisoc.2007.4402492 dblp:conf/vlsi/BalakrishnanE07 fatcat:ncgleqmfqngj5axxfvx76siiui

Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis

Andrew Canis, Jason H. Anderson, Stephen D. Brown
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
Resource sharing is a classic high-level synthesis (HLS) optimization that saves area by mapping multiple operations to a single functional unit.  ...  Multi-pumping is a viable approach to achieve the area reductions of resource sharing, with considerably less negative impact to circuit performance.  ...  [9] investigated the impact of FPGA architecture on resource sharing patterns of interconnected operators.  ... 
doi:10.7873/date.2013.053 dblp:conf/date/CanisAB13 fatcat:x6ehepvwwbcedbmlqumrrthicu

FPGA prototyping of a RISC processor core for embedded applications

M. Gschwind, V. Salapura, D. Maurer
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design.  ...  While previously hardware emulation required massive investment in design effort and special purpose emulators, an emulation approach based on high-density field-programmable gate array (FPGA) devices  ...  The Synopsys and Xilinx XACT tools have been made available to them through the EUROPRACTICE program of the European Commission.  ... 
doi:10.1109/92.924027 fatcat:y2lgnrazwbfchixzfge7kpmbxu

Fast and cycle-accurate modeling of a multicore processor

Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer, Arvind
2012 2012 IEEE International Symposium on Performance Analysis of Systems & Software  
We begin with a cycle-level specification of a multicore architecture which includes realistic in-order cores and detailed models of shared, coherent memory and on-chip network.  ...  In this paper we present Arete, an FPGA-based processor simulator, which offers high performance along with accuracy and modifiability.  ...  Many thanks to all members of the CSG-Arvind group whose valuable input helped us shape the narrative in this paper.  ... 
doi:10.1109/ispass.2012.6189224 dblp:conf/ispass/KhanVBA12 fatcat:o5aewc52p5ecncigfcr663imyu

Challenges and opportunities of ESL design automation

Zhiru Zhang, Deming Chen
2012 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology  
This paper identifies a set of key challenges in ESL design automation with major focus on high-level synthesis (HLS).  ...  System-level synthesis compiles a complex application in a system-level description (such as SystemC) into a set of tasks to be executed on various processors, or a set of functions to be implemented in  ...  We concentrated on resource allocation and binding tasks because they are the key steps to determine the interconnections during high-level synthesis.  ... 
doi:10.1109/icsict.2012.6467670 fatcat:6cium5rwsjhsteh46ip6bnbxjy

A Top-Down Optimization Methodology for Mutually Exclusive Applications

Alp Kilic, Zied Marrakchi, Habib Mehrez
2014 International Journal of Reconfigurable Computing  
It takes the advantage of the possibility of resource sharing as done in FPGA and of predefined multiple functions as in ASIC.  ...  Proliferation of mutually exclusive applications on circuits and the higher cost of silicon make the resource sharing more and more important.  ...  Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper. Acknowledgment This work is partially funded by the ANR project ASTECAS.  ... 
doi:10.1155/2014/827613 fatcat:galfv7bzjrfltlc4tzpwqpr6l4

Ultra-High Performance and Low-Cost Architecture of Discrete Wavelet Transforms [chapter]

Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Safa Saadaoui, Abbas Dandache
2020 Wavelet Theory [Working Title]  
A modulization in VHDL at RTL level and implementation of the designed architecture on FPGA technology in a NexysVideo board (Artix 7 FPGA) are done in this work, where the performance, the configurability  ...  Consequently, to process data in high speed and decrease hardware usage. The different steps of the post/pre-synthesis configurable algorithm are detailed in this paper.  ...  the massif need for hardware resource by: i) intelligent sharing of hardware computing resources (multipliers and adders) among the different filters and stages, ii) design a linear architecture to limited  ... 
doi:10.5772/intechopen.94858 fatcat:osgo2ieegzap5ijd7nflvgqyba

CRUSADE

Bharat P. Dave
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
In this paper, we address the problem of hardware/ software co-synthesis of dynamically reconfigurable embedded systems.  ...  To the best of our knowledge, this is the first co-synthesis algorithm which targets dynamically reconfigurable embedded systems.  ...  Dynamic reconfiguration of FPGA/CPLD can result in low cost architectures due to temporal sharing of resources across multiple functions.  ... 
doi:10.1145/307418.307461 fatcat:6dcuxlzuc5egzhunhzhnitie5y

Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing [article]

Akshay Dua, Yixing Li, Fengbo Ren
2020 arXiv   pre-print
This paper presents Systolic-CNN, an OpenCL-defined scalable, run-time-flexible FPGA accelerator architecture, optimized for accelerating the inference of various convolutional neural networks (CNNs) in  ...  Systolic-CNN is also run-time-flexible in the context of multi-tenancy cloud/edge computing, which can be time-shared to accelerate a variety of CNN models at run time without the need of recompiling the  ...  Fig. 2 shows the high-level system architecture of Systolic-CNN.  ... 
arXiv:2012.03177v1 fatcat:h5alzshjybhv7kmpmeb46an3qm

FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters

Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Juliana Srour, Abbas Dandache
2018 Advances in Science, Technology and Engineering Systems  
These architectures are modeled in VHDL at RTL modeling level. They are generic and fully configurable: at synthesis and post-synthesis.  ...  Furthermore, the impact of tree depth and filters order on throughput is very light due to the linearize architecture of our model.  ...  Moreover, a massive pipeline-parallel DWPT-IDWPT architecture with massive sharing of resources: the core of the architecture is based on sharing hardware resources between P-DWPT and P-IDWPT transforms  ... 
doi:10.25046/aj030516 fatcat:fuj27tzq7zcuxkk6qzbbxjjzfu

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

Rym Skhiri, Virginie Fresse, Jean Paul Jamont, Benoit Suffran, Jihene Malek
2019 International Journal of Reconfigurable Computing  
We present a survey of the cloud FPGA works that have been proposed to exploit the advantages of using FPGA in the cloud.  ...  As more and more FPGA are being deployed in traditional cloud, it is appropriate to clarify what is the cloud FPGA and which drawbacks of using FPGA in local are resolved.  ...  Conflicts of Interest e authors declare that there are no conflicts of interest regarding the publication of this paper.  ... 
doi:10.1155/2019/8085461 fatcat:fnhvx3aqxzev3kqk7psmxkqine

Fast and accurate resource estimation of RTL-based designs targeting FPGAS

Paul Schumacher, Pradip Jha
2008 2008 International Conference on Field Programmable Logic and Applications  
In this paper, we describe a fast and accurate method of estimating the FPGA resources of any RTL-based design.  ...  Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design.  ...  In this paper, we describe a fast FPGA resource estimation tool that can work with any RTL-based tool flow, including high-level synthesis flows that create RTL.  ... 
doi:10.1109/fpl.2008.4629908 dblp:conf/fpl/SchumacherJ08 fatcat:bcurcf6lf5fankcyuvujmugoqe

High-level synthesis for large bit-width multipliers on FPGAs

Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of  ...  We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric.  ...  the high bit-width multiplier on a single FPGA.  ... 
doi:10.1145/1084834.1084890 dblp:conf/codes/QuanDDB05 fatcat:q4tr26aubnbdras3molzsbllti
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