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Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris B. Wilkerson
2007 Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07  
A statistical performance simulator is developed to explore the impact of die-to-die (D2D) and within-die (WID) parameter variations on the distributions of maximum clock frequency (FMAX) and throughput  ...  more variation tolerant than single-core processors due to the larger impact of memory latency and bandwidth on overall throughput.  ...  Conclusion A statistical performance simulator is developed to examine the impact of die-to-die (D2D) and within-die (WID) parameter variations on the distributions of maximum clock frequency (FMAX) and  ... 
doi:10.1145/1283780.1283792 dblp:conf/islped/BowmanASW07 fatcat:d55c3hdyfnh6rm3oyua6z3tjmm

Process variation aware performance modeling and dynamic power management for multi-core systems

Siddharth Garg, Diana Marculescu, Sebastian X. Herbert
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
In this work, we present some promising, recently proposed solutions to mitigate the impact of process variations on multi-core platforms that deal with variability aware performance modeling, and static  ...  Emerging multi-core platforms are increasingly impacted by the manufacturing process variations that introduce core-to-core and chip-to-chip differences in their power and performance characteristics.  ...  variations) and, from one multi-core chip to another (due to D2D variations).  ... 
doi:10.1109/iccad.2010.5654293 dblp:conf/iccad/GargMH10 fatcat:mhb3osfshbeozj4qp7fivo66iq

Characterizing chip-multiprocessor variability-tolerance

Sebastian Herbert, Diana Marculescu
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
Spatially-correlated intra-die process variations result in significant core-to-core frequency variations in chip-multiprocessors.  ...  The improved variability-tolerance of FI-CMPs over their globally-clocked counterparts is quantified across a range of core counts and sizes under constant die area.  ...  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for Throughput degradation from nominal as a function of variation parameters with σ d2d V T H = 0.0%  ... 
doi:10.1145/1391469.1391550 dblp:conf/dac/HerbertM08 fatcat:tt6yy2ksavcj3e6h6f3zuvmhyq

Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variation

Davit Mirzoyan, Sander Stuijk, Benny Akesson, Kees Goossens
2013 The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia  
The novelty of the framework lies in the computation of the probability distribution of throughput, based on a user-specified set of clock-frequency levels per VFI domain considering both within-die and  ...  Variability in the manufacturing process results in variation in the maximum supported frequency of individual cores in a Multi-Processor System-on-Chip (MPSoC).  ...  Parameter variability, in turn, affects the performance characteristics of cores in a Multi-Processor System-on-Chip (MPSoC) [2] .  ... 
doi:10.1109/estimedia.2013.6704497 dblp:conf/estimedia/MirzoyanSAG13 fatcat:kjnwdab2ife5hjyjh6sagryppi

Addressing Process Variations at the Microarchitecture and System Level

Siddharth Garg
2012 Foundations and Trends® in Electronic Design Automation  
[32] and decomposition of the variations on a single die into its die-to-die and within-die components.  ...  The challenge is to develop parameterized macro-models that can be used to determine the distribution of clock frequency and power consumption of a module as a function of process variation and micro-architectural  ... 
doi:10.1561/1000000031 fatcat:qrtycgjfpfakvob4tdp6q5tjpu

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Love Singhal, Sejong Oh, Eli Bozorgzadeh
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints  ...  We provide a case study of configurable Leon processors as the cores implemented on FPGA.  ...  High within-die variations will lead to variations in the performance parameters of different cores on a multiprocessor system.  ... 
doi:10.1145/1450135.1450192 dblp:conf/codes/SinghalOB08 fatcat:23ql6lvi5ndtjmo7yweeck3twe

Scaling with Design Constraints: Predicting the Future of Big Chips

Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron
2011 IEEE Micro  
The last few years have witnessed high-end processors with increasing number of cores and increasingly larger dies.  ...  Voltage scaling techniques, such as near-threshold operation, will be a key determinant on the extent of dark-vs-dim silicon when maximizing chip throughput. 3) Within two technology generations, the gap  ...  Acknowledgments The authors would like to thank Mark Sweet and Michael Floyd at IBM System and Technology Group, also Anne Gattiker, Jente B.  ... 
doi:10.1109/mm.2011.42 fatcat:6ard3cb27zhi3c6prnkunieiqy

Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units

Timothy N. Miller, Renji Thomas, Radu Teodorescu
2012 IEEE computer architecture letters  
Low voltage operation, however, increases the effects of parameter variation resulting in significant frequency heterogeneity between (and within) otherwise identical cores.  ...  Half-Speed Unit (HSU) mitigates within-core variation by halving the frequency of select functional blocks with the goal of boosting the frequency of individual cores, thus raising the frequency ceiling  ...  The authors would like to thank the anonymous reviewers for their suggestions and feedback.  ... 
doi:10.1109/l-ca.2011.36 fatcat:em6v6gkdf5hjjl2wwqrhgn4tsu

Leveraging 3D Technology for Improved Reliability

Niti Madan, Rajeev Balasubramonian
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors.  ...  A potential solution to mitigate the impact of such errors is redundancy via an in-order checker processor.  ...  The isolation of the checker core to a separate die reduces the impact on the leading core's layout, wiring, and cycle time.  ... 
doi:10.1109/micro.2007.31 dblp:conf/micro/MadanB07 fatcat:fujfszg25nfxncpwik2kxfkkh4

Leveraging 3D Technology for Improved Reliability

Niti Madan, Rajeev Balasubramonian
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors.  ...  A potential solution to mitigate the impact of such errors is redundancy via an in-order checker processor.  ...  The isolation of the checker core to a separate die reduces the impact on the leading core's layout, wiring, and cycle time.  ... 
doi:10.1109/micro.2007.4408258 fatcat:prpycpg3wfgwbnhe5tqneewoli

A comparative study of voltage/frequency scaling in NoC

Saeeda Usman, Samee U. Khan, Sikandar Khan
2013 IEEE International Conference on Electro-Information Technology , EIT 2013  
Voltage and frequency is dynamically scaled to produce energy efficient multi-core networkon-chip (NoC).  ...  A detailed analysis of the techniques employed for this purpose are studied and based on the optimized performance the most effective ones are reported.  ...  ACKNOWLEDGMENTS The authors are grateful to Muhammad Awais, Osman Khalid, and Assad Abbas for their valuable suggestions.  ... 
doi:10.1109/eit.2013.6632716 dblp:conf/eit/UsmanKK13 fatcat:o6pxc4vvnjenboa7ljblpnr3ia

Characterizing and evaluating voltage noise in multi-core near-threshold processors

Xuan Zhang, Tao Tong, Svilen Kanev, Sae Kyu Lee, Gu-Yeon Wei, David Brooks
2013 International Symposium on Low Power Electronics and Design (ISLPED)  
In this paper, we provide the first quantitative analysis of voltage noise in multi-core near-threshold processors in a future 10nm technology across SPEC CPU2006 benchmarks.  ...  Lowering the supply voltage to improve energy efficiency leads to higher load current and elevated supply sensitivity.  ...  The clock frequency, die area, and the number of cores of the STC system configuration in Table IV is derived from an Atom core in 45nm technology, which operates at 1.6GHz, consumes 4W TDP, and occupies  ... 
doi:10.1109/islped.2013.6629271 dblp:conf/islped/ZhangTKLWB13 fatcat:fch7jbuwrzdw5drfcc65uzadoa

Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2014 IEEE transactions on computers  
voltage and temperature variations, as well as adapt to the different classes of the instruction sequences.  ...  The adaptive guardbanding technique eliminates traditional guardbands on operating frequency using information from PVT variations and application-specific requirements on computational accuracy.  ...  ACKNOWLEDGMENT This material is based upon work supported by the NSF Variability Expeditions under award n. CCF-1029783, and FP7 ERC-AdG MultiTherman GA n. 291125.  ... 
doi:10.1109/tc.2013.72 fatcat:imbd2almtbcy7gcnjdpxktdapu

Frequency and voltage planning for multi-core processors under thermal constraints

Michael Kadin, Sherief Reda
2008 2008 IEEE International Conference on Computer Design  
In this work, we propose novel methods to find the optimal operating parameters, i.e., frequency and voltage, that maximize a multi-core system throughput under thermal constraints.  ...  Multi-core architectures use multiple cores running at moderate clock frequencies to run several threads concurrently, which increases overall system throughput.  ...  In fact, coding and compiling for TLP is one of the most difficult challenges of multi-core processors.  ... 
doi:10.1109/iccd.2008.4751902 dblp:conf/iccd/KadinR08 fatcat:zxzblz2yr5fvzgx3lxtyrocnpy

Quantifying and coping with parametric variations in 3D-stacked microarchitectures

Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel Loh, Alok Choudhary
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
We take advantage of the layer-to-layer variations to reduce yield losses by splitting critical components among multiple layers.  ...  Their implications on performance and yield are particularly profound on 3D architectures: a defect on even a single layer can render the entire stack useless.  ...  ACKNOWLEDGEMENTS This work was in part supported by NSF grants CCF-0916746, CCF-0747201, and CNS-0720691. We would also like to thank all the anonymous referees for their helpful comments.  ... 
doi:10.1145/1837274.1837312 dblp:conf/dac/OzdemirPDMLC10 fatcat:selbg2e3pjghney3lrer6sdfla
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