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Impact of chip-level integration on performance of OLTP workloads

L.A. Barroso, K. Gharachorloo, A. Nowatzyk, B. Verghese
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)  
In addition, the paper presents a detailed study of the performance impact of chip-level integration in the context of OLTP workloads.  ...  chip-level integration.  ...  Acknowledgments We are grateful to Robert Bosch for developing the out-of-order processor model for the SimOS-Alpha environment.  ... 
doi:10.1109/hpca.2000.824334 dblp:conf/hpca/BarrosoGNV00 fatcat:3mj5v4p2ongk3fwwzs7x5pgfx4

A detailed comparison of two transaction processing workloads

Stets, Gharachorloo, Barroso
2002 2002 IEEE International Workshop on Workload Characterization  
Nonetheless, it turns out that the overall impact of most architectural choices (e.g., out-of-order execution, on-chip integration of system modules, chip multiprocessing) are surprisingly similar for  ...  A number of recent studies have characterized the behavior of transaction processing workloads and proposed architectural features to improve their performance.  ...  Figure 5 . 5 Performance impact of out-of-order processors and chip-level integration (8-processor configuration). Figure 6 . 6 Chip multiprocessing performance.  ... 
doi:10.1109/wwc.2002.1226492 fatcat:b23waf7eivdgvaf2uxyhcpgylm

Piranha

Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
2000 SIGARCH Computer Architecture News  
Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP.  ...  The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising  ...  The following people have also made significant technical contributions to Piranha: Joan Pendleton wrote the initial Verilog for the Alpha core, Dan Scales helped with the inter-chip coherence protocol  ... 
doi:10.1145/342001.339696 fatcat:4vkvpcl3fbbyroknoobobfd4ye

Piranha

Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
2000 Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00  
Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP.  ...  The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising  ...  The following people have also made significant technical contributions to Piranha: Joan Pendleton wrote the initial Verilog for the Alpha core, Dan Scales helped with the inter-chip coherence protocol  ... 
doi:10.1145/339647.339696 fatcat:5j2s3ywecjaeljdv2jsczyb3wa

Data mining on an OLTP system (nearly) for free

Erik Riedel, Christos Faloutsos, Gregory R. Ganger, David F. Nagle
2000 Proceedings of the 2000 ACM SIGMOD international conference on Management of data - SIGMOD '00  
We show that such a scheme makes it possible to support a Data Mining workload on an OLTP system almost for free: there is only a small impact on the throughput and response time of the existing workload  ...  Specifically, we show that an OLTP system has the disk resources to provide a consistent one third of its sequential bandwidth to a background Data Mining task with close to zero impact on OLTP throughput  ...  At low transaction loads, it is possible to achieve an even higher level of background throughput if we allow a small impact (between 25 and 30% impact on transaction response time) on the OLTP performance  ... 
doi:10.1145/342009.335375 dblp:conf/sigmod/RiedelFGN00 fatcat:o6orppfcyrdkphaarkd7wjinqi

Data mining on an OLTP system (nearly) for free

Erik Riedel, Christos Faloutsos, Gregory R. Ganger, David F. Nagle
2000 SIGMOD record  
We show that such a scheme makes it possible to support a Data Mining workload on an OLTP system almost for free: there is only a small impact on the throughput and response time of the existing workload  ...  Specifically, we show that an OLTP system has the disk resources to provide a consistent one third of its sequential bandwidth to a background Data Mining task with close to zero impact on OLTP throughput  ...  At low transaction loads, it is possible to achieve an even higher level of background throughput if we allow a small impact (between 25 and 30% impact on transaction response time) on the OLTP performance  ... 
doi:10.1145/335191.335375 fatcat:yvmwm33kanbubkna7fceyabsyy

ASR: Adaptive Selective Replication for CMP Caches

Bradford Beckmann, Michael Marty, David Wood
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs).  ...  Some CMPs use a shared L2 cache to maximize the on-chip cache capacity and minimize off-chip misses.  ...  thank Luke Yen, Dan Gibson, the Wisconsin Computer Architecture Affiliates, Virtutech AB, the Wisconsin Condor group, the Wisconsin Computer Systems Lab, and the anonymous reviewers for their comments on  ... 
doi:10.1109/micro.2006.10 dblp:conf/micro/BeckmannMW06 fatcat:ybh52lm5ajenvezppy2f2rbjpy

A case for shared instruction cache on chip multiprocessors running OLTP

Partha Kundu, Murali Annavaram, Trung Diep, John Shen
2003 Proceedings of the 2003 workshop on MEmory performance DEaling with Applications , systems and architecture - MEDEA '03  
This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP).  ...  Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors.  ...  Barroso et al [1] first proposed the idea of using a CMP for the express purpose of multiplying OLTP performance on a single chip.  ... 
doi:10.1145/1152923.1024297 fatcat:5wxozscxabfrbiivwyp4a2wfgu

A case for shared instruction cache on chip multiprocessors running OLTP

Partha Kundu, Murali Annavaram, Trung Diep, John Shen
2004 SIGARCH Computer Architecture News  
This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP).  ...  Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors.  ...  Barroso et al [1] first proposed the idea of using a CMP for the express purpose of multiplying OLTP performance on a single chip.  ... 
doi:10.1145/1024295.1024297 fatcat:jfknco5jbfcy3hcpn7luajusna

Virtual hierarchies to support server consolidation

Michael R. Marty, Mark D. Hill
2007 SIGARCH Computer Architecture News  
Third, we show that the best of our two virtual hierarchy (VH) variants performs 12-58% better than the best alternative flat directory protocol when consolidating Apache, OLTP, and Zeus commercial workloads  ...  Second, we develop the paper's central idea of imposing a two-level virtual (or logical) coherence hierarchy on a physically flat CMP that harmonizes with VM assignment.  ...  ACKNOWLEDGEMENTS We thank Philip Wells for providing assistance with simulating consolidated workloads.  ... 
doi:10.1145/1273440.1250670 fatcat:unky5v7mjrgjrkqo6onif4olqm

Virtual hierarchies to support server consolidation

Michael R. Marty, Mark D. Hill
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
Third, we show that the best of our two virtual hierarchy (VH) variants performs 12-58% better than the best alternative flat directory protocol when consolidating Apache, OLTP, and Zeus commercial workloads  ...  Second, we develop the paper's central idea of imposing a two-level virtual (or logical) coherence hierarchy on a physically flat CMP that harmonizes with VM assignment.  ...  ACKNOWLEDGEMENTS We thank Philip Wells for providing assistance with simulating consolidated workloads.  ... 
doi:10.1145/1250662.1250670 dblp:conf/isca/MartyH07 fatcat:vahlmpg2orblnlks4s5xmruj3u

Reducing OLTP instruction misses with thread migration

Islam Atta, Pinar Tözün, Anastasia Ailamaki, Andreas Moshovos
2012 Proceedings of the Eighth International Workshop on Data Management on New Hardware - DaMoN '12  
Online transaction processing (OLTP) suffers from high instruction miss rates since the instruction footprint of OLTP transactions does not fit in today's L1-I caches.  ...  However, modern many-core chips have ample aggregate L1 cache capacity across multiple cores.  ...  in the early days of this work, and the reviewers and Ippokratis Pandis for their constructive comments on the paper.  ... 
doi:10.1145/2236584.2236586 dblp:conf/damon/AttaTAM12 fatcat:wnouvaelcvgtjdlbqkhuy425ju

Databases and hardware

Anastasia Ailamaki
2015 Proceedings of the VLDB Endowment  
Performance is improved with top-of-the line research on data processing algorithms; efficiency, however, is contingent on seamless collaboration between the database software and hardware and storage  ...  maintaining smooth collaboration blossoms into a multitude of interesting research avenues with direct technological impact.  ...  In current mainstream servers, each chip is an Island; as the number of cores on a chip increases, however, soon we will identify Islands within a single chip.  ... 
doi:10.14778/2824032.2824142 fatcat:ugl7ujexjng57fqbebzt3oecre

Spatio-temporal memory streaming

Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi
2009 SIGARCH Computer Architecture News  
Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses.  ...  Because each technique targets a different subset of misses, their effectiveness varies across workloads and each leaves a significant fraction of misses unpredicted.  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their feedback on this paper and members of the SimFlex team at Carnegie Mellon for contributions to our simulation infrastructure  ... 
doi:10.1145/1555815.1555766 fatcat:2a4fvni5yvgoraeiuhonszveju

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors

Brian T. Gold, Babak Falsafi, James C. Hoe
2009 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing  
Our simulation results of commercial workloads indicate average performance overhead is within 4% (9% maximum) of tightly coupled DMR solutions.  ...  Chip-level redundancy in a DSM server faces a key challenge: the increased latency to check results among redundant components.  ...  ACKNOWLEDGEMENTS The authors would like to thank the members of the TRUSS research group at CMU for their feedback on earlier drafts of this paper and the CMU SimFlex team for simulation infrastructure  ... 
doi:10.1109/prdc.2009.39 dblp:conf/prdc/GoldFH09 fatcat:53japsqrezgudlwgduudd4d6zq
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