Filters








1,006 Hits in 4.2 sec

Illustrative Design Space Studies with Microarchitectural Regression Models

Benjamin C. Lee, David M. Brooks
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
We illustrate these capabilities using performance and power models for three studies of a 260,000 point design space: (1) pareto frontier analysis, (2) pipeline depth analysis, and (3) multiprocessor  ...  This approach combines design space sampling and statistical inference to identify trends from a sparse simulation of the space.  ...  Regression models enable a complete characterization of the microarchitectural design space.  ... 
doi:10.1109/hpca.2007.346211 dblp:conf/hpca/LeeB07 fatcat:taaq4z6ojzhjhohhaotrcr5gta

CPR: Composable performance regression for scalable multiprocessor models

Benjamin C. Lee, Jamison Collins, Hong Wang, David Brooks
2008 2008 41st IEEE/ACM International Symposium on Microarchitecture  
Composable performance regression (CPR) fundamentally addresses these intractable multiprocessor simulation times, estimating multiprocessor performance with a combination of uniprocessor, contention,  ...  Furthermore, composable regression is scalable, requiring 0.33x the simulations required by prior regression strategies.  ...  Figure 5 5 illustrates uniprocessor model construction. This model requires N uni samples from the full design space.  ... 
doi:10.1109/micro.2008.4771797 dblp:conf/micro/LeeCWB08 fatcat:di4kfo7yb5emhnzasj73f4bsoi

ACM student research competition reception---Statistical inference for efficient microarchitectural and application analysis

Benjamin C Lee
2006 Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06  
Illustrative design space studies with microarchitectural regression models. HPCA-13: International Symposium on High Performance Computer Architecture, Feb 2007. B.C. Lee and D.M. Brooks.  ...  of 375,000 design points Microarchitectural Analysis Application Analysis Conclusion Methodology Evaluation Case Study Validation Approach Framework Formulate models with 1,000 samples Obtain  ... 
doi:10.1145/1188455.1188591 dblp:conf/sc/Lee06a fatcat:rjn4qy5qqjhmnhyjjrbqwzmm74

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Benjamin C. Lee, David Brooks
2008 ACM SIGOPS Operating Systems Review  
With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips 3 /w efficiency gains of up to 5.3x (median 2.4x) relative to their  ...  In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points.  ...  Benchmarks from models formulated with 500 samples obtained uniformly at random from the design space S.  ... 
doi:10.1145/1353535.1346288 fatcat:msgv727m2zev3k34b3r67ij6xy

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Benjamin C. Lee, David Brooks
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips 3 /w efficiency gains of up to 5.3x (median 2.4x) relative to their  ...  In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points.  ...  Benchmarks from models formulated with 500 samples obtained uniformly at random from the design space S.  ... 
doi:10.1145/1346281.1346288 dblp:conf/asplos/LeeB08 fatcat:5z7g56245rb43gdpyr4p36fhmi

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Benjamin C. Lee, David Brooks
2008 SIGARCH Computer Architecture News  
With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips 3 /w efficiency gains of up to 5.3x (median 2.4x) relative to their  ...  In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points.  ...  Benchmarks from models formulated with 500 samples obtained uniformly at random from the design space S.  ... 
doi:10.1145/1353534.1346288 fatcat:dwcyi42oyndaxekw35qkc5ubhu

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Benjamin C. Lee, David Brooks
2008 SIGPLAN notices  
With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve bips 3 /w efficiency gains of up to 5.3x (median 2.4x) relative to their  ...  In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B points.  ...  Benchmarks from models formulated with 500 samples obtained uniformly at random from the design space S.  ... 
doi:10.1145/1353536.1346288 fatcat:jieodfr7urcpjitskiprxq6n7q

Applied inference

Benjamin C. Lee, David Brooks
2010 ACM Transactions on Architecture and Code Optimization (TACO)  
Specifically, this paradigm (1) defines a large, comprehensive design space, (2) samples points from the space for simulation, and (3) constructs regression models based on sparse simulations.  ...  We illustrate new capabilities in three case studies for a large design space of approximately 260,000 points: (1) Pareto frontier, (2) pipeline depth, and (3) multiprocessor heterogeneity analyses.  ...  Design Space Studies Given the accuracy of regression models, we present applications of performance and power regression modeling to three representative design space studies: -Pareto Frontier Analysis  ... 
doi:10.1145/1839667.1839670 fatcat:4rwuf5ehqjeitheo6n5e6ecbbm

Modeling and Analyzing the Effect of Microarchitecture Design Parameters on Microprocessor Soft Error Vulnerability

Chang Burm Cho, Wangyuan Zhang, Tao Li
2008 2008 IEEE International Symposium on Modeling, Analysis and Simulation of Computers and Telecommunication Systems  
This paper explores using predictive models to analyze and forecast the effect of various processor microarchitecture design parameters on reliability and their tradeoffs with performance.  ...  The increasing chip soft error rates make it is necessary to estimate process transient fault susceptibility at the microarchitecture design stage.  ...  The focus of our work is to develop computationally effective models to reason the correlation of microarchitecture reliability with various architecture parameters at a large design space.  ... 
doi:10.1109/mascot.2008.4770557 fatcat:kkb32g34l5davpp3x5kbopeuxa

Spatial Sampling and Regression Strategies

Benjamin C. Lee, David M. Brooks
2007 IEEE Micro  
The predictive ability and computational efficiency of these regression models enable new capabilities in microarchitectural design space studies.  ...  Collectively, our experiences with this paradigm suggest significant potential for accurate, efficient statistical inference in the microarchitectural domain.  ...  These capabilities produce more comprehensive variants of traditional studies or enable new studies not possible with current usage patterns for microarchitectural simulators.  ... 
doi:10.1109/mm.2007.61 fatcat:glw2ffoyuvf2jb7sf7nnzzojbq

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Chang-Burm Cho, Wangyuan Zhang, Tao Li
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
microprocessors with a microarchitecture design space that consists of 9 key parameters.  ...  Our results show that the models achieve high accuracy in revealing workload dynamic behavior across a large microarchitecture design space.  ...  In this study, we consider a design space that consists of 9 microarchitectural parameters (see Tables 2) of the superscalar architecture.  ... 
doi:10.1109/micro.2007.26 dblp:conf/micro/ChoZL07 fatcat:m2ifdzqnkjfn7l7b4swehetzfy

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Chang-Burm Cho, Wangyuan Zhang, Tao Li
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
microprocessors with a microarchitecture design space that consists of 9 key parameters.  ...  Our results show that the models achieve high accuracy in revealing workload dynamic behavior across a large microarchitecture design space.  ...  In this study, we consider a design space that consists of 9 microarchitectural parameters (see Tables 2) of the superscalar architecture.  ... 
doi:10.1109/micro.2007.4408262 fatcat:ms7d63av6zavziknfzsxr4uczi

Roughness of microarchitectural design topologies and its implications for optimization

Benjamin C. Lee, David Brooks
2008 High-Performance Computer Architecture  
These roughness metrics exhibit noteworthy correlations (1) against regression model error, (2) against non-linearities and non-monotonicities of contour maps, and (3) against the effectiveness of optimization  ...  Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchitectural studies.  ...  Due to computational costs of extensive simulation, we approximate this function with regression models formulated from sparsely simulated design space samples.  ... 
doi:10.1109/hpca.2008.4658643 dblp:conf/hpca/LeeB08 fatcat:6qk4kdluzfhdnkqnnlfip3p3fe

A Predictive Performance Model for Superscalar Processors

P. Joseph, Kapil Vaswani, Matthew Thazhuthaveetil
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters  ...  Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.  ...  For this study, we map the microarchitectural design space to the input space of the RBF network and use CPI as the response.  ... 
doi:10.1109/micro.2006.6 dblp:conf/micro/JosephVT06 fatcat:s653vjt32jdlthcfeq4iystbhy

Characterizing the Effect of Microarchitecture Design Parameters on Workload Dynamic Behavior

Chang-Burm Cho, Wangyuan Zhang, Tao Li
2007 2007 IEEE 10th International Symposium on Workload Characterization  
We then construct error-bounded linear regression models that relate microarchitecture design parameters to various wavelet coefficients that capture workload dynamics at multiresolution levels.  ...  To our knowledge, this paper presents the first work on microarchitecture design space exploration focusing on workload dynamics.  ...  processors with varied microarchitecture design parameters.  ... 
doi:10.1109/iiswc.2007.4362176 dblp:conf/iiswc/ChoZL07 fatcat:gi3ukz3tarcjlhqgqhg2blrbxi
« Previous Showing results 1 — 15 out of 1,006 results