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Identifiers in Registers
[chapter]
2019
Green Chemistry and Sustainable Technology
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The local memory of each process is represented by a finite-state controller and a fixed number of registers, each of which can store the unique identifier of some process in the network. ...
We propose a formal model of distributed computing based on register automata that captures a broad class of synchronous network algorithms. ...
A leader-election algorithm, for instance, takes as input a network and outputs the same network, but with every process storing the identifier of the unique leader in some dedicated register r. ...
doi:10.1007/978-3-030-17127-8_7
dblp:conf/fossacs/BolligBR19
fatcat:sahjrqc6vvbolbarhj5bzerin4
Naming, Assigning and Registering Identifiers in a Locator/Identifier-Split Internet Architecture
2011
International Journal on Advances in Internet Technology
unpublished
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We show how the registration and assignment for identifiers is handled and which modifications in the network stack are necessary. ...
In this work, we give an overview of a scheme how to name identifiers not only for hosts, but basically for anything that needs to be identified in a future Internet. ...
Section 5 demonstrates necessary modifications in the network stack and Section 6 discusses a possible lookup algorithm that tolerates spelling mistakes and allows unsharp queries to a certain extent. ...
fatcat:b3k74lkvmrcydgc6v4dbyrmiqi
Automatic synthesis of clock gating logic with controlled netlist perturbation
2008
Proceedings of the 45th annual conference on Design automation - DAC '08
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Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. ...
Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average. ...
In practice, the overall dynamic power of the logic network is also decreased through the optimizations described in Section 4. ...
doi:10.1145/1391469.1391637
dblp:conf/dac/Hurst08
fatcat:tr27zyruvjgxzhbomfxka3nzou
FPGA implementation of dispatching algorithms for Local Control of Elevator Systems
2008
2008 IEEE International Symposium on Industrial Electronics
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This paper describes the validation of five dispatching algorithms for an elevator system that was implemented on Spartan 3 FGPA based boards in an integrated approach. ...
algorithm to be run in each LCS. ...
The network system is composed of several hardware nodes that implement the physical layer of the network. Each LCS and the FEGCS are connected with the network nodes via a serial interface RS232. ...
doi:10.1109/isie.2008.4677210
fatcat:lkpi4zj2gfeo3ii5vmctfo2al4
Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks
2013
Integration
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With a combination of nonuniform meshes and unbuffered trees (UBT), a variation-tolerant hybrid clock distribution network is produced. ...
The algorithm has been implemented in a standard 65 nm cell library using standard EDA tools, and tested on several benchmark circuits. ...
Acknowledgment The authors would like to thank the VLSI Systems Research Center at the Technion for providing CAD tools, and Virage Logic Corpopration for providing technology process and cell library ...
doi:10.1016/j.vlsi.2012.12.001
fatcat:prtie3qjc5cpzdrkf6rqms265i
Blockchain-IoT Sensor (BIoTS): A Solution to IoT-Ecosystems Security Issues
2021
Sensors
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Blockchain algorithms implemented in IoT hardware opens a path to IoT devices' security and ensures participation in data validation inside a food certification process. ...
BIoTS can participate as a miner in the blockchain network through Smart Contracts and solve security issues related to data integrity and data traceability in an Blockchain-IoT system. ...
BIoTS proposed a block in the network eight times, with humidity and temperature data validated by the nodes of the network described in Figure 11 . ...
doi:10.3390/s21134388
pmid:34206874
fatcat:4avsd5mhcvbgzb4yo5edgzv3yy
Computational Model for the One-Way Quantum Computer: Concepts and Summary
[chapter]
2005
Quantum Information Processing
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The computational model underlying the QC C is different from the quantum logic network model and it is based on different constituents. ...
It has no quantum register and does not consist of quantum gates. The QC C is nevertheless quantum mechanical since it uses a highly entangled cluster state as the central physical resource. ...
In this section we have described the QC C as a simulator of quantum logic networks. We adopted all the network notions such as the "quantum register" and "quantum gates". ...
doi:10.1002/3527603549.ch3
fatcat:sp6koiwarngproh42uc55hcrdy
Computational Model for the One-Way Quantum Computer: Concepts and Summary
[article]
2002
arXiv
pre-print
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The computational model underlying the QCc is different from the quantum logic network model and it is based on different constituents. ...
It has no quantum register and does not consist of quantum gates. The QCc is nevertheless quantum mechanical since it uses a highly entangled cluster state as the central physical resource. ...
In this section we have described the QC C as a simulator of quantum logic networks. We adopted all the network notions such as the "quantum register" and "quantum gates". ...
arXiv:quant-ph/0207183v1
fatcat:4oigsovdqrhapdtewxjdo2h5fm
Computational Model for the One-Way Quantum Computer: Concepts and Summary
[chapter]
2005
Quantum Information Processing
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The computational model underlying the QC C is different from the quantum logic network model and it is based on different constituents. ...
It has no quantum register and does not consist of quantum gates. The QC C is nevertheless quantum mechanical since it uses a highly entangled cluster state as the central physical resource. ...
In this section we have described the QC C as a simulator of quantum logic networks. We adopted all the network notions such as the "quantum register" and "quantum gates". ...
doi:10.1002/3527606009.ch3
fatcat:o5n43y4bkzbczmuhndhskehyqq
A survey on voltage dip events in power systems
2008
The Renewable Energies and Power Quality Journal (RE&PQJ)
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Basic data mining principles were taken as the basis to identify similar steps in power quality works involving classification and knowledge discovery tasks. ...
The objectives to perform voltage dip analysis, activities inside of this analysis and methodological aspects are described from a data mining perspective. ...
The coverage matrix associates the register equipments with each line of the network. ...
doi:10.24084/repqj06.274
fatcat:no6xajgl5nctpmzhi7uidhw2he
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm
2008
Computers & electrical engineering
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The parameter BEARER identifies to each radio bearer among those associated with each user; this input value avoids the use of the same keystream for encryption/decryption in every radio bearer. ...
The importance of the security issues is higher in current cellular networks than in previous systems because users are provided with the mechanisms to accomplish very crucial operations like banking transactions ...
The extension can be used to implement other KASUMIbased algorithms, such as A5/3 and GEA3. This approach can also be adapted to implement other Feistel-like encryption algorithms. ...
doi:10.1016/j.compeleceng.2007.11.003
fatcat:4hvrlqdwujdkheh5p7v63ii6de
Low Power Implementation of Trivium Stream Cipher
[chapter]
2013
Lecture Notes in Computer Science
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This paper describes a low power hardware implementation of the Trivium stream cipher based on shift register parallelization techniques. ...
The design was simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. ...
Section 2 briefly describes the specification algorithm, Trivium. ...
doi:10.1007/978-3-642-36157-9_12
fatcat:sqlpfurlsvhjdogrchz7cnza4a
iFinger: Intrusion Detection in Industrial Control Systems via Register-based Fingerprinting
2020
IEEE Journal on Selected Areas in Communications
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The iFinger utilizes register states to generate ICS fingerprints to detect malicious attacks on industrial networks. ...
Specifically, the boolean logic represents every register state sequence of the ICS controller, and the deterministic finite automaton (DFA) generates a device fingerprint. ...
The algorithm 1 describes the DFA generation of the ICS device. ...
doi:10.1109/jsac.2020.2980921
fatcat:kgn3tsi64nf4tlxwuai5dpzttq
An ultra low power adaptive wavelet video encoder with integrated memory
2000
IEEE Journal of Solid-State Circuits
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A mapping is made between small image blocks (4 4 pixels on the test chip) and PE's, with each PE containing both memory and logic required for its block. ...
algorithmic subcomponents. ...
ALGORITHM The compression algorithm basis is the EZW algorithm reported in [10] , in conjunction with wavelet filters found in [11] and arithmetic coding described in [12] . ...
doi:10.1109/4.839917
fatcat:b3gdmvvdt5gerdn3xgdnqawwaa
LiveCloud: A lucid orchestrator for cloud datacenters
2012
4th IEEE International Conference on Cloud Computing Technology and Science Proceedings
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Leveraging software defined networking (SDN) techniques, LiveCloud further integrates network resources into datacenter orchestration and service provision with improved service-level agreements and faster ...
This paper presents LiveCloud, a management framework for resources in cloud datacenters. ...
Figure 2 shows the logical view in LiveCloud, which is corresponding to the physical view described former. The logical view has a consistent three-layer access topology (logical topology). ...
doi:10.1109/cloudcom.2012.6427544
dblp:conf/cloudcom/WangLQL12
fatcat:p7muz2rflvcvlbndzsktt3wew4
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