159 Hits in 4.8 sec

SEUs Mitigation on Program Counter of the LEON3 Soft Processor

Afef KCHAOU, Wajih EL, Rached TOURKI
2017 International Journal of Advanced Computer Science and Applications  
It starts by evaluating the behavior of LEON3's program counter against Single Event Upset error-rate accuracy between the functional simulation and the FPGA emulation and an analysis of the LEON3 reliability  ...  Different automated fault-injection methods have been developed for evaluating the sensitivity of integrated circuit.  ...  The first one is based on RTL simulations allowing evaluating IC sensitivity against SEU at early design phases, while the second one focuses on FPGA emulation which enables to obtain results closer to  ... 
doi:10.14569/ijacsa.2017.080737 fatcat:eqgmnp5tevcy3dj5b3sxlmnibm

A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

Zahra Kazemi, David Hely, Mahdi Fazeli, Vincent Beroulle
2020 Electronics  
Two of the primary means of fault attacks are clock and voltage fault injection.  ...  Not only do the devices need to be protected against software and network-based attacks, but proper attention must also be paid to recently emerging hardware-based attacks.  ...  They focus on three main type of software-based, emulation-based, and hardware-based fault injection approaches. Then, they explore the requirements for advanced hardware based attacks.  ... 
doi:10.3390/electronics9071153 fatcat:v7besqcahjgbrbtgndlxglwcuq

A Versatile Framework for Implementation Attacks on Cryptographic RFIDs and Embedded Devices [chapter]

Timo Kasper, David Oswald, Christof Paar
2010 Lecture Notes in Computer Science  
An FPGA-based approach enables very accurate timing and flexible adaption to any extension module.  ...  Rather, we illustrate a cost-effective setup that can be tailored to any desired type of security evaluation or penetration test.  ...  Note that the main focus in the following is on the demonstration of the fault injection capabilities, not on the implementation of actual attacks against cryptographical algorithms.  ... 
doi:10.1007/978-3-642-17499-5_5 fatcat:yd7vx5jw5vh2boctlr2z2hjxcm

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security

Wenye Liu, Chip-Hong Chang, Xueyang Wang, Chen Liu, Jason Fung, Mohammad Ebrahimabadi, Naghmeh Karimi, Xingyu Meng, Kanad Basu
2021 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
On the other hand, ML-based approaches have also been adopted by adversaries to assist side-channel attacks, reverse engineer integrated circuits and break hardware security primitives like Physically  ...  the perspective of hardware security.  ...  fault injection attacks.  ... 
doi:10.1109/jetcas.2021.3084400 fatcat:c4wdkghpo5fwbhvkekaysnahzm

The Impact Of Pulsed Electromagnetic Fault Injection On True Random Number Generators

Maxime Madau, Michel Agoyan, Josep Balasch, Milos Grujic, Patrick Haddad, Philippe Maurine, Vladimir Rozic, Dave Singelee, Bohan Yang, Ingrid Verbauwhede
2018 Zenodo  
Within this context, this paper investigates the robustness of TRNGs based on Ring Oscillators (focusing on the delay chain TRNG) against pulsed electromagnetic fault injection.  ...  True Random Number Generators (TRNGs) thus become a relevant entry point for attacks that aim at lowering the security of integrated systems.  ...  One major threat against secure devices is Fault Injection (FI). Different tools can be employed to induce transient faults in Integrated Circuits (IC), each of them having its drawbacks and assets.  ... 
doi:10.5281/zenodo.1434074 fatcat:3r2lv3ei3faknncaa77glhhasa


Antonis Papadogiannakis, Laertis Loutsis, Vassilis Papaefstathiou, Sotiris Ioannidis
2013 Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13  
This way, the attacker will inject invalid code that will fail to execute on the randomized processor.  ...  However, all the existing implementations of ISR are based on emulators and binary instrumentation tools that (i) incur a significant runtime performance overhead, (ii) limit the ease of deployment of  ...  We also thank the Computer Architecture and VLSI Systems Lab of FORTH-ICS for providing access to FPGAs and design tools.  ... 
doi:10.1145/2508859.2516670 dblp:conf/ccs/PapadogiannakisLPI13 fatcat:dyah4eul3nbdlptygdbjtqj4su

Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level

Quentin Forcioli, Jean-Luc Danger, Clementine Maurice, Lilian Bossuet, Florent Bruguier, Maria Mushtaq, David Novo, Loic France, Pascal Benoit, Sylvain Guilley, Thomas Perianin
2021 2021 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)  
This paper introduces an ongoing study aiming at analyzing the attacks relying on the hardware vulnerabilities of the microarchitectures of CPUs and SoCs.  ...  The processors (CPUs) embedded in System on Chip (SoC) have to face recent attacks taking advantage of vulnerabilities/features in their microarchitectures to retrieve secret information.  ...  or fault injection.  ... 
doi:10.1109/eurospw54576.2021.00017 fatcat:ljhuwgh3ebb47ksi3bocapspmy

Security FPGA Analysis [chapter]

E. Wanderley, R. Vaslin, J. Crenne, P. Cotret, G. Gogniat, J.-P. Diguet, J.-L. Danger, P. Maurine, V. Fischer, B. Badrignans, L. Barthe, P. Benoit (+1 others)
2011 Security Trends for FPGAS  
We identify the main vulnerabilities of FPGAs to tackle the security requirements based on the security pyramid concept.  ...  In this chapter we propose an overview of some existing attacks, a classification of attackers and the different levels of security as promoted by the FIPS 140-2 standard.  ...  Therefore cryptographic devices must be protected against fault injection and leakage information.  ... 
doi:10.1007/978-94-007-1338-3_2 fatcat:5iqydsjq4nhbho63ccanv5csxa

Diversity-By-Design for Dependable and Secure Cyber-Physical Systems: A Survey [article]

Qisheng Zhang, Abdullah Zubair Mohammed, Zelin Wan, Jin-Hee Cho, Terrence J. Moore
2020 arXiv   pre-print
; (v) A variety of existing diversity-based approaches based on five different classifications; (vi) The types of attacks mitigated by existing diversity-based approaches; (vii) The overall trends of evaluation  ...  on developing secure and dependable cyber-physical systems (CPSs) using diversity as a system design feature.  ...  [70] used a FPGA mapping tool to evaluate their proposed architectural diversity technique against brute force and side-channel attacks.  ... 
arXiv:2007.08688v1 fatcat:q5umyoql4nfbfhbjlbdhavu72q

Cryptographic Fault Diagnosis using VerFI

Victor Arribas, Felix Wegener, Amir Moradi, Svetla Nikova
2020 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
Among several case studies, we demonstrate its application on an implementation of LED cipher with combined countermeasures against side-channel analysis and fault-injection attacks (published at CRYPTO  ...  While Differential Fault Attacks (DFAs) on symmetric ciphers have been known for over 20 years, recent developments have tried to structurally classify the attackers' capabilities as well as the properties  ...  suggested to evaluate the countermeasures against fault-injection attacks in the literature.  ... 
doi:10.1109/host45689.2020.9300264 fatcat:w3z6atxubrc6rcmbtgzaepqgue

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak
2009 ACM Transactions on Reconfigurable Technology and Systems  
PUF-based security approaches have numerous comparative strengths with respect to traditional cryptography-based techniques, including resilience against physical and side channel attacks and suitability  ...  However, classical delay-based PUF structures have a number of drawbacks including susceptibility to guessing, reverse engineering, and emulation attacks, as well as sensitivity to operational and environmental  ...  We now investigate the security of the proposed PUF against emulation attacks.  ... 
doi:10.1145/1502781.1502786 fatcat:yteu5mg5n5hzzavjk2izlii6uu

The Forgotten Threat of Voltage Glitching: A Case Study on Nvidia Tegra X2 SoCs [article]

Otto Bittner, Thilo Krachenfels, Andreas Galauner, Jean-Pierre Seifert
2021 arXiv   pre-print
Voltage fault injection (FI) is a well-known attack technique that can be used to force faulty behavior in processors during their operation.  ...  At the same time, modern systems on a chip (SoCs) are used in security-critical applications, such as self-driving cars and autonomous machines.  ...  Using the prepared hardware and software setup, fault injection can now be performed to evaluate its effect on the test code.  ... 
arXiv:2108.06131v2 fatcat:7oor7ezryrbevksuyjxa5zhjnm

Hardware and Security [chapter]

Gedare Bloom, Eugen Leontie, Bhagirath Narahari, Rahul Simha
2012 Handbook on Securing Cyber-Physical Critical Infrastructure  
The test phase ensures each IC passes a set of test procedures that check for manufacturing faults based on the known design.  ...  One solution for defending against physical attack is secure coprocessing.  ... 
doi:10.1016/b978-0-12-415815-3.00012-1 fatcat:usk6j5webjdytjmtjublkukjve

M&M: Masks and Macs against Physical Attacks

Lauren De Meyer, Victor Arribas, Svetla Nikova, Ventzislav Nikov, Vincent Rijmen
2018 Transactions on Cryptographic Hardware and Embedded Systems  
Cryptographic implementations on embedded systems need to be protected against physical attacks.  ...  Today, this means that apart from incorporating countermeasures against side-channel analysis, implementations must also withstand fault attacks and combined attacks.  ...  Security against faults is based on the fact that the MAC key α is secret. Without knowledge of α, an adversary cannot forge a valid tag τx for a faultyx.  ... 
doi:10.13154/tches.v2019.i1.25-50 dblp:journals/tches/MeyerANNR19 fatcat:au4febpyh5debexdsqjzirbjke

Digital PUF using intentional faults

Teng Xu, Miodrag Potkonjak
2015 Sixteenth International Symposium on Quality Electronic Design  
Compared to the traditional delay based PUF, the induced defects in circuit are permanent defects that guarantee the fault-based digital PUF resilient against operational variations.  ...  However, one of the most popular hardware security primitive, PUF, has been an analog component.  ...  SECURITY ATTACKS AND EVALUATION In this section, we analysis the security properties of the digital PUF based on adders, multipliers, and XOR networks respectively.  ... 
doi:10.1109/isqed.2015.7085467 dblp:conf/isqed/XuP15 fatcat:ncqonwahsfeoxedjipiscrvobq
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