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Ianus: an Adpative FPGA Computer [article]

Ianus Collaboration: F. Belletti, I. Campos, A. Cruz, L. A. Fernandez, S. Jimenez, A. Maiorano, F. Mantovani, E. Marinari, V. Martin-Mayor, D. Navarro, A. Munoz-Sudupe, S. Perez Gaviro, G. Poli (+7 others)
2005 arXiv   pre-print
In this note we describe Ianus, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability.  ...  The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their  ...  An overview of Ianus Ianus is a massively parallel machine, optimized for the simulation of spinglass systems and based on latest generation FPGA components.  ... 
arXiv:cond-mat/0507270v1 fatcat:rtdyw6pbcvhfbk7ep3ovrposty

Ianus: an adaptive FPGA computer

F. Belletti, I. Campos, A. Maiorano, S.P. Gavir, D. Sciretti, A. Tarancon, J.L. Velasco, A.C. Flor, D. Navarro, P. Tellez, L.A. Fernandez, V. Martin-Mayor (+8 others)
2006 Computing in science & engineering (Print)  
In this note we describe Ianus, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability.  ...  The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their  ...  An overview of Ianus Ianus is a massively parallel machine, optimized for the simulation of spinglass systems and based on latest generation FPGA components.  ... 
doi:10.1109/mcse.2006.9 fatcat:l546kqw5nzgebieh2luoxsce4i

Simulating spin systems on IANUS, an FPGA-based computer

F. Belletti, M. Cotallo, A. Cruz, L.A. Fernández, A. Gordillo, A. Maiorano, F. Mantovani, E. Marinari, V. Martín-Mayor, A. Muñoz-Sudupe, D. Navarro, S. Pérez-Gaviro (+6 others)
2008 Computer Physics Communications  
We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.  ...  We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device.  ...  Poli in the development of the IANUS Ethernet interface is warmly acknowledged.  ... 
doi:10.1016/j.cpc.2007.09.006 fatcat:34stuw7ygnhg5oo5ixkopadkrq