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Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC

Felipe M. Sampaio, Bruno Zatt, Muhammad Shafique, Jorg Henkel, Sergio Bampi
2018 IEEE transactions on circuits and systems for video technology (Print)  
A hybrid scratchpad video memory (Hy-SVM) for energy-efficient Tiles-parallelized High-Efficiency Video Coding (HEVC) is presented herein.  ...  The inter-Tiles data reuse potential of parallel HEVC is exploited by our run-time overlap prediction scheme, which identifies the redundant memory access behavior by analyzing monitored past frames encoding  ...  depicts our hybrid scratchpad video memory architecture (Hy-SVM) and its management layer for parallel HEVC encoding.  ... 
doi:10.1109/tcsvt.2018.2870825 fatcat:uwwx5efrvjfxrmc3phr76zu3r4

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragić, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella (+22 others)
2018 Microprocessors and microsystems  
Acknowledgements This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668.  ...  non-SIMT execution • Advaced mesh-based Network-on-Chip • Lightweight control flow constructs exposed to the programmer • Hybrid memory hierarchy providing both coherent caches and non-coherent scratchpad  ...  We first identified a few kernels that have potentially highly parallel memory accesses and that can benefit from the scratchpad memory support.  ... 
doi:10.1016/j.micpro.2018.05.011 fatcat:gf4jczkxgzcpfdbgqygmwbkwfq

Parallel HEVC Decoding on Multi- and Many-core Architectures

Chi Ching Chi, Mauricio Alvarez-Mesa, Jan Lucas, Ben Juurlink, Thomas Schierl
2012 Journal of Signal Processing Systems  
The results also demonstrate that exploiting more parallelism by increasing the number of cores can improve the energy efficiency measured in terms of Joules per frame substantially.  ...  The results show that our parallel HEVC decoder is capable of achieving an average frame rate of 116 fps for 4k resolution on a standard multicore CPU.  ...  For the Tilera architecture also the scratchpad memory allocated for each thread is locally homed, which improves the cache utilization by having no redundant cache line copies present as long as the decoding  ... 
doi:10.1007/s11265-012-0714-2 fatcat:mdrz5z4xnrc4jpgburphiitivy