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High-performance ethernet-based communications for future multi-core processors

Michael Schlansker, Norman P. Jouppi, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell, Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan Binkert
2007 Proceedings of the 2007 ACM/IEEE conference on Supercomputing - SC '07  
Hardware must be simple for close integration in future multi-core processors. Inexpensive hardware minimizes cost for users with modest communication needs.  ...  The primary contribution of this work is the design, implementation, and evaluation of a network architecture for Ethernet-based communications in future data centers.  ...  The hardware models inexpensive closely attached NICs for future multi-core processors.  ... 
doi:10.1145/1362622.1362672 dblp:conf/sc/SchlanskerCOSRBCMBJ07 fatcat:b6nqg7loczb6bifp5cptihxjgy

High Performance Ethernet Packet Processor Core for Next Generation Networks

Raja Jitendra Nayaka
2012 International Journal of Next-Generation Networks  
Application specific processors require high performance, low power and high degree of programmability is the limitation in many general processor based applications.  ...  This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification  ...  In this paper Ethernet packet processor core is developed to use in SoC application for design of high performance switches, router and other IP based products for next generation networks (NGN).  ... 
doi:10.5121/ijngn.2012.4307 fatcat:izmm5kawabgspd62bonia4p2km

An Experimental Study on How to Build Efficient Multi-core Clusters for High Performance Computing

Luiz Carlos Pinto, Luiz H. B. Tomazella, M. A. R. Dantas
2008 2008 11th IEEE International Conference on Computational Science and Engineering  
Multi-core technology produces a new scenario for communicating processes in an MPI cluster environment and consequently the involved trade-offs need to be uncovered.  ...  Based on previous assertions (4) and (6) , the idle cores of systems A and C seemingly do not indicate great positive effects on performance of either one-way or two-way inter-process communication.  ...  Proposed setup approach High performance computing based on commodities has become feasible with the growing popularity of multi-core technology and Gigabit Ethernet interconnect.  ... 
doi:10.1109/cse.2008.63 dblp:conf/cse/PintoTD08 fatcat:wz7gf5intvhspljwbsiprcul2a

TCP/IP Performance Near I/O Bus Bandwidth on Multi-Core Systems: 10-Gigabit Ethernet vs. Multi-Port Gigabit Ethernet

Hyun-Wook Jin, Yeon-Ji Yun, Hye-Churn Jang
2008 Parallel Processing  
The issues related can be summarized into two: i) Utilizing I/O bus bandwidth for high bandwidth network connection and ii) Utilizing multiple cores for high packet processing throughput.  ...  We, however, also show that the multi-port 1GigE can consume much more processor resource than 10GigE.  ...  In this paper, we focus on the in-depth performance measurement of both 10GigE and multi-port 1GigE. The utilizing multi-processors for high network throughput has been studied in [13, 14] .  ... 
doi:10.1109/icpp-w.2008.33 dblp:conf/icppw/JinYJ08 fatcat:4id3iyxbmvg27faneo3vw5lo5q

A TDMA Ethernet Switch for Dynamic Real-Time Communication

Gonzalo Carvajal, Sebastian Fischmeister
2010 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines  
This permits the user to tailor the communication behavior to the needs of the distributed application with verifiable performance.  ...  A real-time communication medium must provide a special coordination mechanism to guarantee bounded communication delays.  ...  Acknowledgment The authors would like to thank Robert Trausmuth and Kevin Perry for their assistant in the Network Code Processor, Ronald Valenzuela for his work on the PCI and Linux interfaces, and Israel  ... 
doi:10.1109/fccm.2010.27 dblp:conf/fccm/CarvajalF10 fatcat:p6qaclwftzhbzgmzppbh5tqhzq

Performance Evaluation of Soft RoCE over 1 Gigabit Ethernet

Gurkirat Kaur
2013 IOSR Journal of Computer Engineering  
RDMA is an effective technology, which is used for reducing system load & improves the performance.  ...  In this paper, we evaluate the heterogeneous Linux cluster, having multi nodes with fast interconnects i.e. gigabit Ethernet & Soft RoCE.  ...  Conclusion & Future Scope In recent trends High Performance Cluster (HPC) Systems has shown that in future the increase in the performance can only be achieved with the right combination of multi-cores  ... 
doi:10.9790/0661-1548187 fatcat:pcdlvrptlnfabpwuo2ry6de2se

Maximizing Application Performance in a Multi-core, NUMA-Aware Compute Cluster by Multi-level Tuning [chapter]

Gilad Shainer, Pak Lui, Martin Hilgeman, Jeffrey Layton, Cydney Stevens, Walker Stemple, Scot Schultz, Guy Ludden, Joshua Mora, Georg Kresse
2013 Lecture Notes in Computer Science  
better performance for VASP at high core counts Objectives • The following was done to provide best practices -VASP performance benchmarking -Understanding VASP communication patterns -Ways to increase  ...  Special Interest Subgroups Missions • HPC|Scale -To explore usage of commodity HPC as a replacement for multi-million dollar mainframes and proprietary based supercomputers with networks and clusters of  ... 
doi:10.1007/978-3-642-38750-0_17 fatcat:7h2x4lkg4vdlflgepyavtfosua

Development of Prototype for Ethernet port with ARM Cortex-M3 Processor for Web Application

Kavya M P, Dr T C Thanuja, Nishant G Angadi
2015 International Journal of Engineering Research and  
ARM processors have rich features, which are essential for processor to meet the performance parameters.  ...  The paper presents the software and hardware implementation of Ethernet port for web applications.  ...  ARM (Advanced RISC Machine) processors are widely used low power microprocessors whose efficiency and performance is high compared to other processors [1] .  ... 
doi:10.17577/ijertv4is090288 fatcat:2ipgccw4kzdzzfb2he6jurjxxa

SPARTA roadmap and future challenges

Enrico Fedrigo, Robert Donaldson, Brent L. Ellerbroek, Michael Hart, Norbert Hubin, Peter L. Wizinowich
2010 Adaptive Optics Systems II  
For AO systems under development, SPARTA provides an implementation for all those functional blocks that are mapped to currently available technologies.  ...  SPARTA, the ESO Standard Platform for Adaptive optics Real Time Applications, provides a generic decomposition in functional blocks that can be applied, unchanged, to a variety of different AO systems,  ...  We therefore identified the need of considering more aggressive solutions in several domains, from the high performance computing units (from CPUs, to GPUs and FPGAs), to the interconnect technology (10  ... 
doi:10.1117/12.857109 fatcat:duwzscrdyzdbjnlvxsdmqvdfiy

Virtual base station pool

ZhenBo Zhu, Parul Gupta, Qing Wang, Shivkumar Kalyanaraman, Yonghua Lin, Hubertus Franke
2011 Proceedings of the 8th ACM International Conference on Computing Frontiers - CF '11  
Such platforms are programmer-friendly and with recent advances on multi-core and hybrid architectures, allow signal processing, network processor class packet processing, wire-speed computation and server-class  ...  We also present the first working prototype of a virtual BS (VBS) pool, exploring the systems challenges in supporting a VBS pool on multi-core IT platforms.  ...  For both scenarios, the hardware resources are allocated fairly. One VBS will use two physical CPU cores of the multi-core system.  ... 
doi:10.1145/2016604.2016646 dblp:conf/cf/ZhuGWKLF11 fatcat:swzqm4ftxzcf5oyhgtd2vz5zgi

An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA

Trio Adiono, Rian Ferdian, Febri Dawani, Imran Abdurrahman, Rachmad Vidya Wicaksana Putra, Nur Ahmadi
2018 Journal of ICT Research and Applications  
This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz.  ...  communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer.  ...  Kresno Adityowibowo, who has contributed to the Ethernet driver part related to this work.  ... 
doi:10.5614/itbj.ict.res.appl.2018.12.1.5 fatcat:ror7fpoy6bcqficwv4prdu3lxy

oc-approach for Safety-oriented Multi-channel Communication in Industrial Application of Human-robot-collaboration (HRC)

2020 International Journal of Computers  
The design and prototyping of a multi-channel communication FPGA-based development board is presented.  ...  Furthermore, the FPGA implementation of SoC with multiple Ethernet MAC interfaces based on various soft cores is demonstrated.  ...  ACKNOWLEDGEMENTS We acknowledge Federal Ministry of Education and Research (BMBF) for financial support (Project number 16SV7815).  ... 
doi:10.46300/9108.2020.14.10 fatcat:q332dxkvxzcrpkfrjsk7zhbjvu

State-of-the-Art and Trends for Computing and Interconnect Network Solutions for HPC and AI

A. Tekin, A.Tuncer Durak, C. Piechurski, D. Kaliszan, F. Aylin Sungur, F. Robertsén, P. Gschwandtner
2021 Zenodo  
Since 2000, High Performance Computing (HPC) resources have been extremely homogeneous in terms of underlying processors technologies.  ...  However, it becomes obvious, looking at the last TOP500, that new trends tend to bring new microarchitectures for General Purpose Processors (GPPs) and new heterogeneous architectures, combining accelerators  ...  Ethernet For a long time, the standard single lane multi-gigabit Ethernet was based on 10 Gbps, with 4 such links being used to create a 40 Gbps link.  ... 
doi:10.5281/zenodo.5717283 fatcat:irgzrdxr6ncijcfxsdb3sdodii

Design of a Multipurpose Whitebox Networking Platform

Nam-Seok Ko, Hwanjo Heo, Sung-Jin Moon, Sung-Kee Noh, Jong-Dae Park, Hong-Shik Park
2013 International Journal of Future Computer and Communication  
Instead of relying on two extreme ends; ASIC or general purpose CPU, we propose a multipurpose platform which combines the moderate flexibility and rich features for fast packet processing of high-performance  ...  for the system.  ...  and is still high enough for general network systems. 5) TCAM Interface: NP-4 supports a TCAM interface which is useful for fast lookups through large tables with wildcards such as multi-field packet classification  ... 
doi:10.7763/ijfcc.2013.v2.175 fatcat:uk4in3mjzjdsvnmkompvwslqkm

Parallel performance prediction for numerical codes in a multi-cluster environment

Giuseppe Romanazzi, Peter K. Jimack
2008 International Multiconference on Computer Science and Information Technology  
We propose a model for describing and predicting the performance of parallel numerical software on distributed memory architectures within a multi-cluster environment.  ...  to be extremely accurate and robust with respect to both the processor and communications architectures considered.  ...  We also thank anonymous referee for their comments concerning Grid meta-scheduling.  ... 
doi:10.1109/imcsit.2008.4747284 dblp:conf/imcsit/RomanazziJ08 fatcat:ehoadagkpjc3fmj6b723p7gn6u
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