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Electronic System-Level Synthesis Methodologies

A. Gerstlauer, C. Haubelt, A.D. Pimentel, T.P. Stefanov, D.D. Gajski, J. Teich
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
With ever increasing system complexities, all major semiconductor roadmaps have identified the need for moving to higher levels of abstraction in order to increase productivity in electronic system design  ...  Based on these observations, we can identify such common principles and needs as they are leading towards and are ultimately required for a true ESL synthesis solution, covering the whole design process  ...  ACKNOWLEDGMENTS Besides the authors, a large number of people are responsible for, or have contributed to, the work described in Section III of this paper.  ... 
doi:10.1109/tcad.2009.2026356 fatcat:vkvmjvxvvrbx5n3xnvbrjaerl4

Heterogeneous System-level Specification Using SystemC

Eugenio Villar, Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel
2008 2008 Design, Automation and Test in Europe  
This has led to the concept of MPSoC (Multi-Processor System-on-Chip) platforms.  ...  This tutorial discusses several key questions with significant impact on the future of MPSoC: What are the MPSoC killer applications? Is homogeneous or heterogeneous architecture the right choice?  ...  Current high-level design methodologies targeting architecture and system levels still assume a classic static timing behaviour and do not include effects of variability on performance or energy.  ... 
doi:10.1109/date.2008.4484641 dblp:conf/date/VillarJGK08 fatcat:b5g4eczeubhd5khp3f2ppdfl5y

Architecture Support for Task Out-of-Order Execution in MPSoCs

Chao Wang, Xi Li, Junneng Zhang, Peng Chen, Yunji Chen, Xuehai Zhou, Ray C.C. Cheung
2015 IEEE transactions on computers  
In order to solve the problem, this paper proposes a novel high level architecture support for automatic out-of-order (OoO) task execution on FPGA based heterogeneous MPSoCs.  ...  The middleware has been verified by the prototype built on FPGA platform.  ...  It dynamically parallelizes the execution of suitably-written sequential programs, in a dataflow fashion on multiple processing cores.  ... 
doi:10.1109/tc.2014.2315628 fatcat:a3s6avcrf5aajgny4qffgicvya

D2.3: System Architecture

Christoforos Kachris, Angelos Bilas, Nikos Chrysos, Hans Vandierendonck
2017 Zenodo  
are developed for the efficient integration of the hardware platforms.  ...  This document presents part of the deliverable on system architecture which aims at describing the overall architecture of VINEYARD and specifically the hardware and the software components that are developed  ...  Each node in the platform can host a typical high performance general purpose processor, a dataflow engine, an FPGA-based server or an MPSoC-based server.  ... 
doi:10.5281/zenodo.898155 fatcat:gjqv2gfngfev3bmmrlxycgzv64

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Ilkka Hautala, Jani Boutellier, Olli Silven
2019 IEEE transactions on computers  
together with a high level of automation in software and hardware design.  ...  However, programming of parallel systems can be time-consuming and challenging if only low-level programming methods are used.  ...  ACKNOWLEDGMENTS The work was partially funded by the Academy of Finland project 309693 UNICODE and Tauno Tönning Foundation.  ... 
doi:10.1109/tc.2019.2937867 fatcat:bkhi52rqkbhivdvtffztgp2424

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC

Leonardo Suriano, Alfonso Rodriguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre
2017 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
In this paper, a design flow that combines, on one side, PREESM, a dataflow-based prototyping framework and, on the other side, Xilinx SDSoC, an HLS-based framework to automatically generate and manage  ...  An image processing application is used as a proof of concept, showing the interoperability possibilities of both tools, the level of design automation achieved and, for the resulting computing architecture  ...  High Level Synthesis (HLS) tools have finally paved the path from high-level languages to HW, allowing some flexibility in selecting the levels of parallelism that HW accelerators should have.  ... 
doi:10.1109/recosoc.2017.8016151 dblp:conf/recosoc/SurianoRDPT17 fatcat:xm25wzrud5hudipi4yypxzqi3u

DKPN: A Composite Dataflow/Kahn Process Networks Execution Model

Paul-Antoine Arras, Didier Fuin, Emmanuel Jeannot, Samuel Thibault
2016 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)  
ACKNOWLEDGMENTS Thanks are due to Arthur Stoutchinin from STMicroelectronics for helpful discussions and numerous insights, as well as Alain Girault for his thorough review of the model, especially the  ...  (2) supporting heterogeneous platforms, including hybrid Von Neumann/dataflow architectures [4] ; (3) capturing the highest level of application dynamism.  ...  In the longer term, integrating DKPN with some high-level synthesis tool would ease the generation of hardware filters with proper interfaces.  ... 
doi:10.1109/pdp.2016.34 dblp:conf/pdp/ArrasFJT16 fatcat:ghe36y2bkrazpcrlbgv6edb5rq

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Mostafa W. Numan, Braden J. Phillips, Gavin S. Puddy, Katrina Falkner
2020 IEEE Access  
BEHAVIOURAL HIGH-LEVEL SYNTHESIS (HLS) 2A High-Level Synthesis (HLS) allows developers to define hardware using a HLL (e.g. C, C++ or SystemC).  ...  compute-intensive parts of an application as high-level dataflow representations.  ... 
doi:10.1109/access.2020.3024098 fatcat:hk7s2deq6zgp5fnuwvm5k6jodu

A compilation flow for parametric dataflow

Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles
2014 Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14  
Parametric dataflow models aim at providing sufficient dynamicity to model new applications, while at the same time maintaining the high level of analyzability needed for efficient real life implementations  ...  results illustrate our compilation flow applied to compilation of 3GPP LTE-Advanced demodulation on a heterogeneous MPSoC with distributed scheduling features.  ...  A new high level format for expressing parametric dataflow graphs based on semi-static actors.  ... 
doi:10.1145/2656106.2656110 dblp:conf/cases/DardaillonMRMC14 fatcat:2mgcsosqlzejpdtvwyru5jasbm

Combined system synthesis and communication architecture exploration for MPSoCs

M. Lukasiewycz, M. Streubuhr, M. Glass, C. Haubelt, J. Teich
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
platforms.  ...  To cope with the huge complexity of the design space, a transformation of the transaction level model to a graph-based model and symbolic representation that allows multi-objective optimization is presented  ...  Exploration From a system synthesis point of view, the problem of mapping a dataflow model specified at transaction level to an MPSoC implementation is defined by the following steps: 1.  ... 
doi:10.1109/date.2009.5090711 dblp:conf/date/LukasiewyczSGHT09 fatcat:ofj5piowvnhwzmhtx2qwzn5zzi

MP-Tomasulo

Chao Wang, Xi Li, Junneng Zhang, Xuehai Zhou, Xiaoning Nie
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
, therefore to operate out-of-order task execution on heterogeneous units.  ...  The promising results show MP-Tomasulo enables programmers to uncover more task-level parallelism on heterogeneous systems, as well as to ease the burden of programmers.  ...  This article proposes MP-Tomasulo, a task-level out-of-order execution model for sequential programs on FPGA-based MPSoC.  ... 
doi:10.1145/2459316.2459320 fatcat:cysm7u5bsvgvdfrwb5ynfjh3sy

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Aurelien Bloch, Simone Casale-Brunet, Marco Mattavelli
2022 Journal of Low Power Electronics and Applications  
The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units.  ...  The synthesis stage of dataflow programs is usually supported by automatic code generation tools.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/jlpea12030036 fatcat:hkcy3sfoxvaczdjqxsrr2dabxu

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

Yue Liu, M engMeng Cao, Kong Jie
2016 International Journal of Future Generation Communication and Networking  
The majority of recent embedded systems are based on MPSoCs (Multi-Processors System on Chip) architectures.  ...  The goal of our algorithm is to replace the static data flow subnetwork by a single dynamic data flow actor such that the global performance in terms of latency and throughput is optimized.  ...  However, the high parallelism of multiple processors makes programming of MPSoCs a challenging task.  ... 
doi:10.14257/ijfgcn.2016.9.9.16 fatcat:clxibco5urce3ffiu5hud3qgdu

StreamBlocks: A compiler for heterogeneous dataflow computing (technical report) [article]

Endri Bezati, Mahyar Emami, Jörn Janneck, James Larus
2021 arXiv   pre-print
This work introduces StreamBlocks, an open-source compiler and runtime that uses the CAL dataflow programming language to partition computations across heterogeneous (CPU/accelerator) platforms.  ...  When an investigation requires rewriting part of the system in a new language or with a new programming model, its high cost can retard the study of different configurations.  ...  Janneck is funded by the ELLIIT program of the Swedish government.  ... 
arXiv:2107.09333v1 fatcat:kw2iszud6fhyxlczkesqqeymai

Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)

Jerónimo Castrillón-Mazo, Tei-Wei Kuo, Heike E. Riel, Matthias Lieber, Marc Herbstritt
2017 Dagstuhl Reports  
The main goal of the seminar 17061 "Wildly Heterogeneous Post-CMOS Technologies Meet Software" was to discuss bridges between material research, hardware components and, ultimately, software for information  ...  The end of exponential scaling in conventional CMOS technologies has been forecasted for many years by now.  ...  As programming abstraction, we use dataflow programming models, architecture models and compilers to automatically generate low-level code for heterogeneous multi-cores [4] .  ... 
doi:10.4230/dagrep.7.2.1 dblp:journals/dagstuhl-reports/MazoKRL17 fatcat:ive75xhpbvgwfb5hdavdixhkpu
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