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The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
[chapter]
2004
Lecture Notes in Computer Science
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This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40 ...
It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. ...
between pipelining (a system-level design optimization) and clustering (a lower-level design optimization), and determine how the degree of pipelining affects the effectiveness of the lower-level CAD ...
doi:10.1007/978-3-540-30117-2_73
fatcat:m67dyai3cnbffnu5wkqutchtci
An optimal low-power/high performance DDP-based Cobra-H64 cipher
2007
Proceedings of the 3rd International ICST Conference on Mobile Multimedia Communications
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A new layout design for a data dependent permutation (DDP)-Cobra H64-bit cipher optimized for low-power and high speed operation is presented in this paper. ...
Through the technique of pipelining in the internal rounding blocks of the Cobra cipher and an increase in the frequency of the circuit from 90MHz to 140MHz, the design achieves increased speed and performance ...
The proposed design including the layout level optimization achieves a frequency of at least 130 MHz. ...
doi:10.4108/icst.mobimedia2007.1915
dblp:conf/mobimedia/RjoubMK07
fatcat:tenrjyphnngv3bd4olumshz7mu
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
2010
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction - SLIP '10
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total energy for set of parallel wires
Max-TPA (high-performance application)
Optimize throughput-per-area for single pipelined wire
Reduce total area for set of parallel wires
Max-TPEA ...
) [Jantsch 2003]
Our work
Wires are pipelined to meet required clock period (throughput)
Explore the power-saving of pipelined interconnects with more
design freedoms
Optimize for different ...
doi:10.1145/1811100.1811118
dblp:conf/slip/ZhangBC10
fatcat:4fbbakqb3fdh3mgicptftyb33m
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
[article]
2021
arXiv
pre-print
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While offering rich optimization opportunities and a high level abstraction, HIR enables sharing of optimizations, utilities and passes with software compiler infrastructure. ...
HIR combines high level language features, such as loops and multi-dimensional tensors, with programmer defined explicit scheduling, to provide a high-level IR suitable for DSL compiler pipelines without ...
Figure 2 . 2 Example
7. 1 1 Loop pipelining Loop pipelining is a key optimization in high level synthesis. ...
arXiv:2103.00194v1
fatcat:vwv7jfr2ofgxjih7uamqxvv4xe
A NOVEL VLSI ARCHITECTURE OF HIGH SPEED 1D DISCRETE WAVELET TRANSFORM
2015
International Journal of Electronics and Electical Engineering
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Firstly we design the high speed linear phase FIR filter using pipelined and parallel arithmetic methods. This proposed filter employs efficiently distributed D-latches and multipliers. ...
The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has high performance and is suitable for portable and high speed devices. ...
We were applying, the multiple low level optimizations in an organized way to improve the performance and reduce the complexity of the design. ...
doi:10.47893/ijeee.2015.1147
fatcat:cchrmviod5hb3lhtzsz7m6nvqa
INTACTE
2007
Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07
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Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. ...
It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraints given as inputs. ...
Co-designing interconnects early along with other components when high level architectural design trade-offs are being made is highly desirable for high level synthesis of embedded SoCs. ...
doi:10.1145/1289881.1289923
dblp:conf/cases/NagpalMBS07
fatcat:umxfwvarrbaapkyg2pdncm2yh4
PACT HDL: A Compiler Targeting Asics and Fpgas with Power and Performance Optimizations
[chapter]
2002
Power Aware Computing
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Chip fabrication technology continues to plunge deeper into submicron levels requiring hardware designers to utilize everincreasing amounts of logic and shorten design time. ...
PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System ...
, system designers require increasingly high-level tools to keep up. ...
doi:10.1007/978-1-4757-6217-4_9
fatcat:eo7dydaktzggfnmyk5k65tc4ha
PACT HDL
2002
Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02
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Chip fabrication technology continues to plunge deeper into submicron levels requiring hardware designers to utilize everincreasing amounts of logic and shorten design time. ...
PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System ...
, system designers require increasingly high-level tools to keep up. ...
doi:10.1145/581630.581659
dblp:conf/cases/JonesBPTCB02
fatcat:m53rpuulhbfdznitqgf346ktwe
PACT HDL
2002
Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02
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Chip fabrication technology continues to plunge deeper into submicron levels requiring hardware designers to utilize everincreasing amounts of logic and shorten design time. ...
PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System ...
, system designers require increasingly high-level tools to keep up. ...
doi:10.1145/581656.581659
fatcat:lvv4oacngvdszlonxjtkciarbm
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages
2013
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
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Work remains to be done on improving and better controlling the tool flow, and on reducing overheads in link-level pipelining. ...
Our solution provides a unique direct comparison with a state-of-the-art synchronous design (xpipesLite), and demonstrates significant overall cost benefits -including highlighting that high-performance ...
HIGH-SPEED DIGITAL PIPELINES The goal of this research is to develop a set of practical asynchronous pipeline circuit structures to support the design of high-performance systems. ...
doi:10.1109/async.2013.29
dblp:conf/async/LiuNS13
fatcat:pgi4on5mbffj3fylrygmhghspy
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
[article]
2021
arXiv
pre-print
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Even with the help of high-level synthesis (HLS), accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve the optimal performance. ...
AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. ...
In general, there are three levels of optimization that one needs to employ to get to a high-performance FPGA design. ...
arXiv:2009.14381v2
fatcat:d4ynz74pubd4pnpko2nvkowqke
High-Level Synthesis: Productivity, Performance, and Software Constraints
2012
Journal of Electrical and Computer Engineering
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However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. ...
Such tools reduce design effort: high-level descriptions are more compact and less error prone. ...
Acknowledgments This paper is supported by the Advanced Digital Sciences Center (ADSC) under a grant from the Agency for Science, Technology, and Research of Singapore. ...
doi:10.1155/2012/649057
fatcat:lvu2kniyyvaa7prpklymhslf5m
Automatic Low Power Optimizations during ADL-driven ASIP Design
2006
2006 International Symposium on VLSI Design, Automation and Test
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ern pipelined embedded processors. ...
Architecture Description Languages (ADLs) offer the ASIP design-With increasing design complexity, automatic clock gating tools ers a quick and optimal design convergence by automatically gener-are getting ...
ADL Structure Overview
Top-level Design
In this section, a brief overview of the architecture description
Pipeline
language LISA is provided. ...
doi:10.1109/vdat.2006.258140
fatcat:ntckq22pnraqdpekaxsieat7ey
A proposed synthesis method for Application-Specific Instruction Set Processors
2015
Microelectronics Journal
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The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms ...
configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. ...
Acknowledgment The work reported in the paper has been developed in the framework of the project "Talent care and cultivation in the scientific workshops of BME". ...
doi:10.1016/j.mejo.2015.01.001
fatcat:6gu6fd2stnbpvcpfugaku3cnje
Improving high level synthesis optimization opportunity through polyhedral transformations
2013
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '13
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State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. ...
High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. ...
HLS offers automated translation from high level languages (e.g., C,C++, SystemC, Haskell and CUDA) to register transfer level (RTL) implementations to reduce the design effort, automated optimization ...
doi:10.1145/2435264.2435271
dblp:conf/fpga/ZuoLLRCC13
fatcat:iedoyxskbvewniwpqon7brpwzm
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