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Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems [chapter]

Nikolaos Kroupis, Dimitrios Soudris
2010 IFIP Advances in Information and Communication Technology  
Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these  ...  In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory  ...  Acknowledgments This work was partially supported by 03ED593 research project, implemented within the framework of the "Reinforcement Programme of Human Research Manpower" (PENED) and co-financed by National  ... 
doi:10.1007/978-3-642-12267-5_14 fatcat:f6efzal235cevcnbh3i7x3kjtu

Energy-monitoring tool for low-power embedded programs

Dongkun Shin, Hojun Shim, Yongsoo Joo, Han-Saem Yun, Jihong Kim, Naehyuck Chang
2002 IEEE Design & Test of Computers  
When developing low-power embedded programs, programmers have specific requirements for energy-monitoring tools. I The tool should produce accurate analysis results reasonably fast.  ...  The tool should give accurate results so that programmers can make correct decisions for reducing a program's energy consumption. Further, because  ...  Acknowledgments We thank Hyung Gyu Lee and Yongseok Choi for their assistance in developing the SES hard-  ... 
doi:10.1109/mdt.2002.1018129 fatcat:fqtye3bl3nehdacb322jfj4ql4

Multiprocessor System-on-Chip (MPSoC) Technology

W. Wolf, A.A. Jerraya, G. Martin
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.  ...  This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture.  ...  ACKNOWLEDGMENT The authors would like to thank B. Ackland and S. Dutta for the helpful discussions of their MPSoCs.  ... 
doi:10.1109/tcad.2008.923415 fatcat:p37pvh5iezfdjd4acepney4zmy

PAM-SoC: A Toolchain for Predicting MPSoC Performance [chapter]

Ana Lucia Varbanescu, Henk Sips, Arjan van Gemund
2006 Lecture Notes in Computer Science  
The paper includes a set of PAM-SoC validation experiments, as well as two sets of experiments to show how PAM-SoC can be used for either application tuning or MPSoC platform tuning in early system design  ...  This paper introduces PAM-SoC, a light-weight performance predictor for MPSoC system-level performance.  ...  We would like to thank Paul Stravers and Philips Research for providing the Wasabi simulator, and for the help and support we got for understanding the details of the architecture, support that allowed  ... 
doi:10.1007/11823285_12 fatcat:szsp62k2mbfrfa6kq7nbqv6jmu

MPSoC power estimation framework at transaction level modeling

Rabie Ben Atitallah, Smail Niar, Jean-Luc Dekeyser
2007 2007 Internatonal Conference on Microelectronics  
In this paper, we present an MPSoC power modeling framework at the Timed Programmer View (PVT) level that offers a good performance/power tradeoff to be found early in the design flow.  ...  The effectiveness of our method is illustrated through a DSE for a parallelized version of H.263 encoder application.  ...  In our platform, this power model is used to deduce the total consumption of the data memory, instruction memory and FIFO buffer components. B.  ... 
doi:10.1109/icm.2007.4497703 fatcat:a22ikcpcrrhglldyqzn4pajoba

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

M. Miranda, C. Ghez, C. Kulkarni, F. Catthoor, D. Verkest
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
The ever increasing gap between processor and memory speeds has motivated the design of embedded systems with deeper cache hierarchies.  ...  To avoid excessive miss rates, instead of using bigger cache memories and more complex cache controllers, program transformations have been proposed to reduce the amount of capacity and conflict misses  ...  High-level address transformations also have a positive effect on memory accesses and in L1-misses both for I-caches and D-caches.  ... 
doi:10.1145/500001.500027 fatcat:p4c7bmg4cnhc3aj4s3fkguw3ki

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

M. Miranda, C. Ghez, C. Kulkarni, F. Catthoor, D. Verkest
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
The ever increasing gap between processor and memory speeds has motivated the design of embedded systems with deeper cache hierarchies.  ...  To avoid excessive miss rates, instead of using bigger cache memories and more complex cache controllers, program transformations have been proposed to reduce the amount of capacity and conflict misses  ...  High-level address transformations also have a positive effect on memory accesses and in L1-misses both for I-caches and D-caches.  ... 
doi:10.1145/500024.500027 fatcat:olgsgvq6pbfkdlitnlsddyx2pu

A Flexible Tool for Estimating Applications Performance and Energy Consumption Through Static Analysis

Charalampos Marantos, Konstantinos Salapas, Lazaros Papadopoulos, Dimitrios Soudris
2021 SN Computer Science  
The design requirements of modern applications that target embedded systems, such as the need for high performance and low energy consumption, impose challenges on developers.  ...  can add estimation models for various platforms.  ...  Acknowledgements This work has received funding from the European Union's Horizon 2020 research and innovation programme under Grant agreement No. 780572 SDK4ED (https ://www.sdk4e d.eu)  ... 
doi:10.1007/s42979-020-00405-7 fatcat:sfm56rsrbrfgtapluf7pqif6qy

Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor

M. K.Jain, Deepak Gour
2012 International Journal of Computer Applications  
An Application Specific Instruction set Processor (ASIP) is a processor designed for a particular application or for a set of applications.  ...  This paper is an attempt to survey and compare both the mentioned techniques of design space exploration of ASIP.  ...  The strategy focuses on exploration of the architectural parameters of the processor, memory subsystem and bus, making up the hardware kernel of a parameterized SOC platform for the design of embedded  ... 
doi:10.5120/6098-8290 fatcat:p2byhxibpzc77fu37s7z57rmny

Hardware/software co-design for energy-efficient seismic modeling

Jens Krueger, David Donofrio, John Shalf, Marghoob Mohiyuddin, Samuel Williams, Leonid Oliker, Franz-Josef Pfreund
2011 Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '11  
chip design optimized for high-order wave equations called "Green Wave."  ...  These results point to the enormous potential energy advantages of our hardware/software co-design methodology.  ...  We also thank Marty Deneroff who has provided a lot of advice and expertise on system design trade-offs and cost models for practical implementation.  ... 
doi:10.1145/2063384.2063482 dblp:conf/sc/KruegerDSMWOP11 fatcat:o2e6edp2ybcaxb6z3bs5wrovji

Fast Trace Generation of Many-Core Embedded Systems with Native Simulation [article]

David Castells-Rufas, Jordi Carrabina, Pablo González de Aledo Marugán, Pablo Sánchez Espeso
2014 arXiv   pre-print
Late availably of hardware platforms, their usual low visibility and controllability, and their limiting resource constraints makes early performance estimation an attractive option instead of using the  ...  Embedded Software development and optimization are complex tasks.  ...  ACKNOWLEDGMENTS This work was partly supported by the European cooperative ITEA2 projects 09011 H4H and 10021 MANY, the CATRENE project CA112 HARP, the Spanish Ministerio de Economía y Competitividad project  ... 
arXiv:1406.4840v1 fatcat:2lztuoqp2raabgxvktwy6gzywe

A Precise High-Level Power Consumption Model for Embedded Systems Software

Mostafa E. A. Ibrahim, Markus Rupp, Hossam A. H. Fahmy
2011 EURASIP Journal on Embedded Systems  
In this paper, we present a precise high-level power estimation methodology for the software loaded on a VLIW processor that is based on a functional level power model.  ...  The increasing demand for portable computing has elevated power consumption to be one of the most critical embedded systems design parameters.  ...  Acknowledgments This work has been funded by the Christian Doppler Laboratory for Design Methodology of Signal Processing Algorithms as well as the COMET K-Project Embedded Computer Vision (ECV) in conjunction  ... 
doi:10.1155/2011/480805 fatcat:ufwrxb27dfgf7epdjfy2hzbclu

Plug-in of power models in the StepNP exploration platform

Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano
2004 Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '04  
In this paper, we propose a power/performance estimation layer designed for StepNP, a system-level architecture simulation and exploration platform for Network Processors and Multi-Processor Systems-on-Chip  ...  This framework is intended to be used at different levels of the design, considering several levels of accuracy and taking full advantage of the StepNP performance profiling features.  ...  The proposed methodology to plug-in power models in a high-level platform has been designed to be easily retargetable to other Hw/Sw co-design frameworks.  ... 
doi:10.1145/1023833.1023847 dblp:conf/cases/BeltramePSS04 fatcat:nmblpfydbrchdes36cpdmuitju

System design methodologies for a wireless security processing platform

S. Ravi, A. Raghunathan, N. Potlapally, M. Sankaradass
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
We present the system-level design methodology used to design a programmable security processor platform for next-generation wireless handsets.  ...  Our system-level design methodology enables the eficient co-design of optimal cryptographic algorithms and an optimized system architecture.  ...  We would like to thank the members of the Tensilica support team for their invahable assistance with the use of the Xtensa processor and tools.  ... 
doi:10.1109/dac.2002.1012728 fatcat:cxmvphy47jh6bai6irlyrb33na

System design methodologies for a wireless security processing platform

Srivaths Ravi, Anand Raghunathan, Nachiketh Potlapally, Murugan Sankaradass
2002 Proceedings - Design Automation Conference  
We present the system-level design methodology used to design a programmable security processor platform for next-generation wireless handsets.  ...  Our system-level design methodology enables the eficient co-design of optimal cryptographic algorithms and an optimized system architecture.  ...  We would like to thank the members of the Tensilica support team for their invahable assistance with the use of the Xtensa processor and tools.  ... 
doi:10.1145/513918.514113 dblp:conf/dac/RaviRPS02 fatcat:5hxbotaczbevxlvmvu2sr64nd4
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