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Multi-Stream LDPC Decoder on GPU of Mobile Devices [article]

Roohollah Amiri, Hani Mehrpouyan
2018 arXiv   pre-print
However, their broad adoption has been hindered by the high complexity of the LDPC decoder.  ...  In this paper, we propose a multi-stream LDPC decoder designed for a mobile device.  ...  In these set of experiments, an x86 CPU processor is the host. V. CONCLUSION A stream-based approach for GPU-based LDPC decoding on embedded devices was introduced in this paper.  ... 
arXiv:1812.06545v1 fatcat:5xpi5rmh7nduxpv6n525fqt3xu

Multi-Stream LDPC Decoder on GPU of Mobile Devices

Roohollah Amiri, Hani Mehrpouyan
2019 2019 IEEE 9th Annual Computing and Communication Workshop and Conference (CCWC)  
However, their broad adoption has been hindered by the high complexity of the LDPC decoder.  ...  In this paper, we propose a multi stream LDPC decoder designed for a mobile device.  ...  In these set of experiments, an x86 CPU processor is the host. A stream-based approach for GPU-based LDPC decoding on embedded devices was introduced in this paper.  ... 
doi:10.1109/ccwc.2019.8666615 dblp:conf/ccwc/AmiriM19 fatcat:dntf2f7rtremlnfka5op7cgpo4

Comparison of parallelization strategies for min-sum decoding of irregular LDPC codes

Hua Xu, Wei Wan, Wei Wang, Jun Wang, Jiadong Yang, Yun Wen
2013 Tsinghua Science and Technology  
The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units  ...  LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years.  ...  Tests show that the LDPC decoder can be implemented on generalpurpose multi-processor or multicore PC platforms using the MSA on multicore platforms with OpenMP or on a GPU using CUDA.  ... 
doi:10.1109/tst.2013.6678903 fatcat:ags3raehhjgyhmbwrik34vgh24

GPU accelerated scalable parallel decoding of LDPC codes

Guohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro
2011 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)  
This paper proposes a flexible low-density paritycheck (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput.  ...  jobs among multi-processors in GPU.  ...  An alternative is to employ graphics processors to perform baseband processing, which can achieve higher computational performance than x86 processors by using many more cores.  ... 
doi:10.1109/acssc.2011.6190388 dblp:conf/acssc/WangWSC11 fatcat:vs6254ad5vdexg6jctandg6mpe

Multicore implementation of LDPC decoders based on ADMM algorithm

Imen Debbabi, Nadia Khouja, Fethi Tlili, Bertrand Le Gal, Christophe Jego
2016 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
High-throughput multi-core LDPC decoders based on x86 processor.  ...  Fig. 5 . 5 Speed up factor: fast decoder throughput Vs original decoder on a single core processor for different LDPC codes.  ...  The parallelism levels available for SPMD parallelization ๏ INTEL Core-i7 has many physical cores having each a SIMD unit, ๏ Switching to many-core devices ?  ... 
doi:10.1109/icassp.2016.7471820 dblp:conf/icassp/DebbabiKTGJ16 fatcat:ntmo7fs6qjek5ay7lrhgfuf5yq

Real-time DVB-S2 LDPC decoding on many-core GPU accelerators

Gabriel Falcao, Joao Andrade, Vitor Silva, Leonel Sousa
2011 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize.  ...  By performing simultaneous multicodeword decoding and adopting special data structures, experimental results show that throughputs superior to 90 Mbps can be achieved when LDPC decoders for the DVB-S2  ...  The host is based on an Asus P6T7 Workstation running the GNU/Linux kernel 2.6.31-22 x86 64.  ... 
doi:10.1109/icassp.2011.5946824 dblp:conf/icassp/FernandesASS11 fatcat:dn62v7o2mvhebjlrlcao52qabm

High Throughput and Low Cost LDPC Reconciliation for Quantum Key Distribution [article]

Haokun Mao, Qiong Li, Qi Han, Hong Guo
2019 arXiv   pre-print
The main contribution of the research is the design of a quantized LDPC decoder including improved RCBP-based check node processing and saturation-oriented variable node processing.  ...  Although most studies about reconciliation of QKD focus on how to improve the efficiency, throughput optimizations have become the highlight in high-speed QKD systems.  ...  Quantized RCBP-based LDPC decoder In this section, a high throughput and efficiency LDPC decoder is proposed.  ... 
arXiv:1903.10107v1 fatcat:nmbokbhuqrcmxngmnf4p7ep24e

Energy consumption analysis of software polar decoders on low power processors

Adrien Cassagne, Olivier Aumage, Camille Leroux, Denis Barthou, Bertrand Le Gal
2016 2016 24th European Signal Processing Conference (EUSIPCO)  
A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps.  ...  A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems.  ...  The low-power general purpose ARM32 and ARM64 processor test-beds based on big.LITTLE architecture are selected as representative of modern multi-core and heterogeneous architectures.  ... 
doi:10.1109/eusipco.2016.7760327 dblp:conf/eusipco/CassagneALBG16 fatcat:ozz4wpazofftligx4ny6dkbbta

High Performance Error Correction for Quantum Key Distribution using Polar Codes [article]

Paul Jouguet, Sébastien Kunz-Jacques
2013 arXiv   pre-print
of the same codes on high-end Graphic Processing Units (GPUs).  ...  Thanks to recursive decoding, they exhibit excellent decoding speed, much higher than large, irregular Low Density Parity Check (LDPC) codes implemented on similar hardware, and competitive with implementations  ...  The polar decoding performance has to be compared with the speed of a LDPC decoder based on BP.  ... 
arXiv:1204.5882v3 fatcat:n7oh4gxzkfh4zhq55inkp7hzem

Fast List Decoders for Polar Codes

Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2016 IEEE Journal on Selected Areas in Communications  
In this paper, we present a new algorithm based on unrolling the decoding tree of the code that improves the speed of list decoding by an order of magnitude when implemented in software.  ...  is worse than that of other modern codes such as low-density parity-check (LDPC) codes.  ...  Table IV compares the speed of LDPC and polar-CRC decoders when decoding that many bits on an Intel Core i7-2600 with turbo frequency boost enabled.  ... 
doi:10.1109/jsac.2015.2504299 fatcat:ixg6ofpgvrfithvn33a42bhzwu

Open Wireless System Cloud: An Architecture for Future Wireless Communications System

Jianwen Chen, Xiang Chen, Jing Liu, Ming Zhao
2012 Network and Communication Technologies  
Open Wireless System Cloud (OWSC) is a radio access network architecture for future wireless communication systems with remote radio heads, centralized wireless computation on open platforms, and cooperative  ...  Centralized open computing platform provides greater flexibility as the system can simultaneously support multi-standards and services, such as 2G, 3G and 4G as well as multiple type wireless applications  ...  Almost all of these computing tasks are implemented by software on N-core general-purpose processors utilizing high degree of parallelism and specially designed accelerators.  ... 
doi:10.5539/nct.v1n2p28 fatcat:ftby5gjyuvc2hjrdddjefpgroy

Low area FPGA Implementation of Secure MIMO OFDM based Wireless ECG Signal Transmission

Santhosh Basavaraj, Malnad College of Engineering, Bangalore Sujatha, Malnad College of Engineering
2021 International Journal of Intelligent Engineering and Systems  
Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) is widely used to provide high speed data transmission and spectrum efficiency in modern wireless communication systems  ...  Moreover, the possibility of retrieving the ECG signals by the adversary is high, when the ECG signal is not secured based on the cryptographic processor.  ...  Here, two different types of LDPC model were created for describing the inherent computational parallelism. An extended version of x86 LDPC decoder was the first LDPC decoder model.  ... 
doi:10.22266/ijies2021.0831.06 fatcat:5yaagmbaxzdplpd6kpyc6jv2de

Extreme Software Defined Radio – GHz in Real Time [article]

Eugene Grayver, Alexander Utter
2020 arXiv   pre-print
Data rates in the low Mbps can be processed on low-power ARM processors, and much higher data rates can be supported on large x86 processors. The advantages of all-software development (vs.  ...  The continuing march of Moore's law makes real-time signal processing on general purpose processors feasible for a large set of waveforms.  ...  The performance of this decoder on different modern GPPs is reported in [6] . BENCHMARKING The throughput was measured on a few modern processors.  ... 
arXiv:2001.03645v1 fatcat:bbeq4us2zra5xmpwnvsqsqli2e

An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes [chapter]

Adrien Cassagne, Bertrand Le Gal, Camille Leroux, Olivier Aumage, Denis Barthou
2016 Lecture Notes in Computer Science  
As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market.  ...  Error Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits.  ...  a multi-core CPUs (x86, ARM).  ... 
doi:10.1007/978-3-319-29778-1_19 fatcat:6agthwrp7jeanlfu46tdzlndeq

Nuberu: Reliable RAN Virtualization in Shared Platforms [article]

Gines Garcia-Aviles, Andres Garcia-Saavedra, Marco Gramaglia, Xavier Costa-Perez, Pablo Serrano, Albert Banchs
2021 Zenodo  
this, maximize network throughput.  ...  Indeed, we show in this paper that the baseline architecture of a base station¿s distributed unit (DU) collapses upon moments of deficit in computing capacity.  ...  sharing 5 Intel Xeon x86 cores @ 1.9GHz.  ... 
doi:10.5281/zenodo.5599122 fatcat:p4mgru76efg7bcyvw6gsy4fsom
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