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Multi-Stream LDPC Decoder on GPU of Mobile Devices [article]

Roohollah Amiri, Hani Mehrpouyan
2018 arXiv   pre-print
However, their broad adoption has been hindered by the high complexity of the LDPC decoder.  ...  Although to date, dedicated hardware has been used to implement low latency LDPC decoders, recent advancements in the architecture of mobile processors have made it possible to develop software solutions  ...  ARM-based SDR systems have been proposed in recent years [10] , [13] with the goal of developing an SDR based LDPC decoder that provides high throughput and low latency on a low-power embedded system  ... 
arXiv:1812.06545v1 fatcat:5xpi5rmh7nduxpv6n525fqt3xu

Multi-Stream LDPC Decoder on GPU of Mobile Devices

Roohollah Amiri, Hani Mehrpouyan
2019 2019 IEEE 9th Annual Computing and Communication Workshop and Conference (CCWC)  
However, their broad adoption has been hindered by the high complexity of the LDPC decoder.  ...  Although to date, dedicated hardware has been used to implement low latency LDPC decoders, recent advancements in the architecture of mobile processors have made it possible to develop software solutions  ...  ARM-based SDR systems have been proposed in recent years [10] , [13] with the goal of developing an SDR based LDPC decoder that provides high throughput and low latency on a low-power embedded system  ... 
doi:10.1109/ccwc.2019.8666615 dblp:conf/ccwc/AmiriM19 fatcat:dntf2f7rtremlnfka5op7cgpo4

A low-cost serial decoder architecture for low-density parity-check convolutional codes

S. Bates, Zhengang Chen, L. Gunthorpe, A.E. Pusane, K.Sh. Zigangirov, Daniel J. Costello
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor.  ...  We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs).  ...  CONCLUSION We have proposed a memory-based serial decoder architecture for LDPC-CCs, which is suitable for LDPC-CCs with large code memory and for low-cost low-power designs.  ... 
doi:10.1109/tcsi.2008.918002 fatcat:2xgyexdltfbdfnh5vomkamxkvq

Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor

JaWone A Kennedy, Daniel L Noneaker
2012 EURASIP Journal on Wireless Communications and Networking  
A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism.  ...  ; the inter-cluster communications latency is a significant factor in limiting the throughput of the decoder.  ...  Higher absolute throughput may be obtained with stream processors fabricated in newer process technologies using more recent architectural innovations for low-power, embedded processors with high SIMD  ... 
doi:10.1186/1687-1499-2012-141 fatcat:mp6xa5ehrrg2bfrgflxtr4cbie

GPU accelerated scalable parallel decoding of LDPC codes

Guohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro
2011 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)  
This paper proposes a flexible low-density paritycheck (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput.  ...  To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding  ...  We can see that the decoder can achieve high throughput, which can greatly speed up the simulation of LDPC decoders.  ... 
doi:10.1109/acssc.2011.6190388 dblp:conf/acssc/WangWSC11 fatcat:vs6254ad5vdexg6jctandg6mpe

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shuai Shao, Peter Hailes, Tsang-Yi Wang, Jwo-Yuh Wu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo
2019 IEEE Communications Surveys and Tutorials  
We show that the overall implementation complexity of turbo, LDPC and polar decoders depends on numerous other factors beyond their computational complexity.  ...  However, the 3GPP standardization group has recently debated whether it should be replaced by Low Density Parity Check (LDPC) or polar codes in 5G New Radio (NR), ultimately reaching the decision to adopt  ...  High at low coding rates Lower for most coding rates Information throughput Low.  ... 
doi:10.1109/comst.2019.2893851 fatcat:rv2p4a4ol5c2dneveopxsxwqqq

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

Youn Sung Park, David Blaauw, Dennis Sylvester, Zhengya Zhang
2014 IEEE Journal of Solid-State Circuits  
Index Terms-Embedded DRAM, LDPC code, LDPC decoder architecture, low-power DSP design. 0018-9200  ...  The majority of the power consumption of a highthroughput LDPC decoder is spent on memory.  ...  Lee for advice on designing the eDRAM, and E. Yeo and P. Urard for suggestions on the LDPC decoder design.  ... 
doi:10.1109/jssc.2014.2300417 fatcat:4vklf6okezeudnmobmjdugeqye

A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

Chiu-Wing Sham, Xu Chen, Francis C. M. Lau, Yue Zhao, Wai M. Tam
2013 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code.  ...  The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate  ...  Rate-5/6 LDPCCC decoders of different sub-matrix sizes have been implemented on an Altera FPGA with our proposed architecture. It is found that our decoders can achieve a throughput of 2.0 Gb/s.  ... 
doi:10.1109/tcsi.2012.2230506 fatcat:idgqjwmvgnforfyqo3k5fkkfai

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 IEEE Journal of Solid-State Circuits  
An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented.  ...  throughput.  ...  He is also active in various aspects of high-speed networking, system-on-chip design technology, very low power designs, and multimedia signal processing.  ... 
doi:10.1109/jssc.2007.916610 fatcat:jxzk7hs2yfbsfhenqn7bebc7du

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2013 Handbook of Signal Processing Systems  
The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient.  ...  The huge computation and high throughput requirements make it very difficult to implement a high throughput LDPC decoder on a general purpose DSP.  ... 
doi:10.1007/978-1-4614-6859-2_23 fatcat:totrkiocljf4ni72xbsgboybdm

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2010 Handbook of Signal Processing Systems  
The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient.  ...  The huge computation and high throughput requirements make it very difficult to implement a high throughput LDPC decoder on a general purpose DSP.  ... 
doi:10.1007/978-1-4419-6345-1_13 fatcat:bgppdcjc5zafdd4q2bwinepy2a

Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder

Si-Yun J. Li, Tyler L. Brandon, Duncan G. Elliott, Vincent C. Gaudet
2012 2012 IEEE Workshop on Signal Processing Systems  
In this thesis, we present an FPGA implementation of parallel-node low-density-paritycheck convolutional-code (PN-LDPC-CC) encoder and decoder.  ...  For a E b /N 0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10 −10 and achieves an energyper-coded-bit of 1.683 nJ based on raw power  ...  BER performance depends on several factors: the LDPC code that the decoder is based on, the number of iterations (each implemented as a physical decoder processor core in the case of LDPC-CC), the bit-precision  ... 
doi:10.1109/sips.2012.50 dblp:conf/sips/LiBEG12 fatcat:ilteilhcijbexfka7aabf5giwe

Iterative decoder architectures

Engling Yeo, B. Nikolic, V. Anantharam
2003 IEEE Communications Magazine  
Applications with low power or high throughput requirements will need to have low constraint lengths.  ...  Implementation was optimized for low power. 500 Mb/s high throughput MAP decoder is theoretically feasible Custom ASIC (Analog) Parallel Analog MAP decoder in BiCMOS Interleavers not included.  ... 
doi:10.1109/mcom.2003.1222729 fatcat:aqa7i42rojfxhdtau3tony3cqq

On using the cyclically-coupled QC-LDPC codes in future SSDs

Qing Lu, Chiu-Wing Sham, Francis C. M. Lau
2016 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)  
Due to their limitapproaching decoding ability, low-density parity-check (LDPC) codes are seen as one of the most promising substitute for the traditional BCH codes, though implementation barriers remain  ...  as well as throughput.  ...  We found this design also a match as a solution for the demanding reliability-enhancing problem in SSDs because it features nonexistent or extremely low error floor, high throughput and economical complexity  ... 
doi:10.1109/apccas.2016.7804048 dblp:conf/apccas/LuSL16 fatcat:fmneszrvmjh67px4v436ilmzxa

Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard

Sabooh Ajaz, Hanho Lee
2014 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)  
This paper presents an area-efficient multi-Gbps multi-mode LDPC decoder architecture for 60GHz wireless gigabit communications.  ...  The proposed architecture shows much better throughput, as well as better area-and energyefficiency, compared to other multi-mode LDPC architectures.  ...  This paper proposes an area-efficient, high-throughput multimode QC-LDPC decoder architecture based on a novel one's complement scheme. II.  ... 
doi:10.1109/apccas.2014.7032742 dblp:conf/apccas/AjazL14 fatcat:5a4t2oiyrraf5ehk77vlixy7aq
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