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A Review on Implementation of Parallel Prefix Adders using FPGA'S

S. Lakshmipriya
2017 International Journal of Trend in Scientific Research and Development  
They produce the high efficiency of the layout using the FPGA analysis. Better delay and performance of RCA design in the 128 bits in the use of the fast array.  ...  The paper mainly used in the implementation of parallel prefix adders using FPGA'S. The carry adders constitute spanning tree adder, sparse Kogge Stone & Kogge-Stone adder.  ...  In the proposed approach a high speed parallel prefix adder is proposed. In the proposed methodology, a high speed kogge stone adder is realized using high speed adder logic.  ... 
doi:10.31142/ijtsrd7165 fatcat:mjblymbnavaxfj6rs3czj2t4qm

A Novel Decimal Arithmetic Operations By using FPGA Logic Block Architecture

C. Mythile, A. Basheeth, R. Logarasu
2022 International Journal of Engineering Technology and Management Sciences  
To improve the efficiency of decimal computation functions in Field-Programmable Gate Array (FPGAs) are used by Hardened adder and carry logic.  ...  For the fast output of decimal operations, devoted tackle units have been proposed and designed in Field Programmable Gate Array.Compared to former architectures, my perpetration results show that the  ...  [11] Field Programmable Gate Arrays (FPGAs) combine limited cost and reconfigurabilitywith high integration capability and performances.  ... 
doi:10.46647/ijetms.2022.v06i04.0034 fatcat:h25mryaminfzvhylmllcgnc5q4

An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier

Thamizharasan .V, Parthipan.V Parthipan.V
2012 International Journal of Computer Applications  
CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder.  ...  Index Terms-Computation sharing, dual transition skewed logic, programmable finite impulse response (FIR) filter.  ...  The MUX using passtransistor logic was implemented to achieve a compact and high-speed design.  ... 
doi:10.5120/8631-1939 fatcat:gkikmw5vpfaczfqsbuepxhzaam

VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

Joo
2012 American Journal of Applied Sciences  
CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder.  ...  The proposed method presents a programmable digital Finite Impulse Response (FIR) filter for high-performance applications.  ...  The MUX using pass-transistor logic was implemented to achieve a compact and high-speed design.  ... 
doi:10.3844/ajassp.2012.2028.2045 fatcat:3kchpvvhljh2fj7fbvsooollau

Design FPGA-Based CL-Minimum Control Unit

Farzin Piltan, Omid Avatefipour, Samira Soltani, Omid Mahmoudi, Mahmoud Reza Safaei Nasrabad, Mehdi Eram, Zahra Esmaeili, Sara Heidari, Kamran Heidari, Mohammad Mahidi Ebrahimi
2016 International Journal of Hybrid Information Technology  
Design a 4 bits Field Programmable Gate Array (FPGA)-based carry lookahead MCU is the main challenging works.  ...  Most of controllers need real time mobility operation so one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA).  ...  An FPGA consists of a uniform array of programmable logic structures that are interconnected by a configurable routing grid.  ... 
doi:10.14257/ijhit.2016.9.1.10 fatcat:alcuft7mafgnfirn7kqgzq4i5a

A New Field Programmable Gate Array: Architecture and Implementation

Hanjin Cho Cho, Young Hwan Bae Bae, Nak Woong Eum Eum, Inhag Park Park
1995 ETRI Journal  
Programmable logic devices (PLDs), which are arrays of programmable logic arrays (PLAs) with programmable interconnections, offer high speed but limited logic gate capacity and limited logic design flexibility  ...  ABSTRACT A new architecture of field programmable gate array for high-speed datapath applications is presented.  ... 
doi:10.4218/etrij.95.0195.0023 fatcat:2ga4fjoeobakvhhtjjdlhdggbq

Efficient FIR filter architectures suitable for FPGA implementation

J.B. Evans
1994 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
field-programmable gate array (FPGA).  ...  By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single  ...  While the ripple carry structure does limit performance, most recent FPGA architectures support high speed carry logic which minimizes the problem. 2 FPGA Implementation An FIR filter tap as shown  ... 
doi:10.1109/82.298385 fatcat:jgfz75mbyjbqfki35m3yp2ghuu

FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase

Abhay Sharma
2015 International Journal of Computer Applications  
Tree Multipliers are frequently used to reduce the delay of array multipliers. The objective of tree multipliers is to utilize the concept of carry save adders in reducing the partial product.  ...  Two well known tree multipliers Wallace and Dadda uses full adders and half adders for the aforesaid purpose.  ...  FPGA IMPLEMENTATION A field programmable gate array (FPGA) is a logic device that contains a two dimensional array of generic logic cells and programmable switches.  ... 
doi:10.5120/20430-2760 fatcat:5tmavaxpy5boxnd7nrwslgvqvq

Implementation Of Unsigned Multiplier Using Area-Delay-Power Efficient Adder

Nalina R, Ashwini S S, Dr. M Z Kurian
2015 Zenodo  
This design will be developed using Verilog programming language and implementing using Field Programmable Gate Array (FPGA) platform.  ...  Accurate operation of the shift and add multiplier is mainly influenced by the performance of the adder. So performance of the adder enhances the performance of the multiplier.  ...  There are many proposed methods and high speed and each logic design has its own advantages in terms of speed and power. All complex and simple digital multiplication is based on addition.  ... 
doi:10.5281/zenodo.33100 fatcat:uhnyiu6avrgi7dmj2ax3zbezsy

A Novel High Speed FPGA Architecture for FIR Filter Design

Sachin B. Jadhav, Nikhil Niwas Mane
2012 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Word and bit level parallelism allows high sampling rates, limited only by the full adder delay.  ...  Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array  ...  By exploiting this architecture using higher compressor for computation addition operation, the constraints on the coefficient values, this architecture yields extremely efficient and high speed programmable  ... 
doi:10.11591/ijres.v1.i1.pp1-10 fatcat:kb4f7kzrdbchndk66lhru6ru4q

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

Sachin B. Jadhav, Jayamala K. Patil, Ramesh T. Patil
2013 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is  ...  Increasing the speed of operation is achieved by using higher modified compressors in critical path.  ...  By exploiting this architecture using higher compressor for computation addition operation, the constraints on the coefficient values, this architecture yields extremely efficient and high speed programmable  ... 
doi:10.11591/ijres.v2.i1.pp15-20 fatcat:tjyhlbnupbghdp3z4hqonbbwve

Transmission Gate base Programmable Binary Incrementer Decrementer

Jaikaran Singh, Mukesh Tiwari, Zuber Khan
2015 International Journal of Computer Applications  
We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle.  ...  The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs.  ...  The circuit can be design by using low power high speed adders and a toggle flipflop base asynchronous counter logic circuit.  ... 
doi:10.5120/19894-1909 fatcat:aksyzyax2nb4poakkkgz5greim

Design Of High Speed Fir Filter On Fpga By Using Multiplexer Array Optimization In Da-Obc Algorithm

Palepu Mohan Radha Devi, Vijay Kumar Chenchela, Palepu Vijayasanthi, Nellore Kapileswar
2016 Zenodo  
This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs).  ...  Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the digital FIR filter.  ...  CONCLUSION This paper is mainly for the high speed of fir filter.  ... 
doi:10.5281/zenodo.50382 fatcat:hkrmcwx5njb4dasayk5p7kbb2y

Low Power CMOS Look-Up Tables using PROM

Thadigotla Venkata Subbareddy, Chakka Sri Harsha Kaushik, Har Narayan Upadhyay, V. Elamaran
2015 Indian Journal of Science and Technology  
Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution.  ...  But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.  ...  This kind of Filed-Effect Transistors (FET) programmable array are the most powerful in the aspect of area.  ... 
doi:10.17485/ijst/2015/v8i22/79164 fatcat:cljqqe6vbbaj5oczfghf3c7uje

Programmable High Speed 8-Bit Binary Incrementer Decrementer
English

Jaikaran Singh, Mukesh Tiwari, Zuber Khan
2015 International Journal of Engineering Trends and Technoloy  
We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle.  ...  The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs.  ...  hence, is commonly used as a basic building block for generic adder arrays.  ... 
doi:10.14445/22315381/ijett-v19p222 fatcat:sqp2b2bg7zacvapyyqpqvdeby4
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