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Hardware Implementation of Modified RC4 Stream Cipher Using FPGA

Jaya Dofe
2012 IOSR Journal of Engineering  
In this project work, an efficient hardware Implementation of modified RC4 stream-cipher is proposed.  ...  The RC4 stream cipher works in two phases. The key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key.  ...  The various encryption algorithms are available but RC4 encryption algorithm is stream type and can be implemented in hardware and software. The RC4 stream cipher is implemented in hardware by P.  ... 
doi:10.9790/3021-026114471450 fatcat:lfoiidqny5e25ovyddldiuxima

State of the Art Realistic Cryptographic Approaches for RC4 Symmetric Stream Cipher

Disha Handa, Bhanu Kapoor
2014 International Journal on Computational Science & Applications  
This paper presents an analysis of available hardware/software parallel implementations of RC4 symmetric key-based algorithm and some security approaches which make it more secure.  ...  RC4 has been used as the data encryption algorithm for many applications and protocols including the Wi-Fi, Skype, and Bit Torrent to name a few.  ...  That means adding more number of cores in hardware will not require any change in algorithm. R.prabu presents "Architecture of High Performance Rc4 Cipher For safe Communication".  ... 
doi:10.5121/ijcsa.2014.4403 fatcat:kuq6tievtfhnrixs4ijortu63u

Implementation of Modified RC4 Algorithm for Wireless Sensor Networks on CC2431

B Kiruthika, R. Ezhilarasie, A. Umamakeswari
2015 Indian Journal of Science and Technology  
RC4 is one of the commonly used stream cipher due to its speed and simplicity in implementation. The drawback of RC4 is weakness in the permutation of internal state table during initial phase.  ...  To overcome the limitations in existing RC4, RC4 stream cipher with modified state table is proposed. The system reduces the known outputs of the internal state and also improves the execution speed.  ...  Stream ciphers are suitable for networks that involve handling of unknown data or continuous transmission of data. RC4 is a stream ciphers 5 that is widely used and is often implemented in software.  ... 
doi:10.17485/ijst/2015/v8is9/65573 fatcat:oouzmgdcwzeipeci2aluxdimkq

Efficient FPGA Implementation of the RC4 Stream Cipher using Block RAM and Pipelining

Eyad Taqieddin, Ola Abu-Rjei, Khaldoon Mhaidat, Raed Bani-Hani
2015 Procedia Computer Science  
RC4 is a popular stream cipher, which is widely used in many security protocols and standards due to its speed and flexibility.  ...  In this paper, a new hardware implementation of the RC4 algorithm using FPGA is proposed.  ...  RC4 is mostly implemented in software but there were several proposed approaches for high-performance hardware implementations of the algorithm.  ... 
doi:10.1016/j.procs.2015.08.306 fatcat:3o33cx4ctrhzpecrmtckqw4t7q


Mohamed Nabil, Alaa Eldin Rohiem
2007 International Conference on Aerospace Sciences and Aviation Technology  
In this work, a proposed hardware implementation of RC4 algorithm on field programmable gate arrays (FPGAs) is introduced.  ...  The design was described using the hardware description language VHDL (Very high speed integrated circuit hardware description language).  ...  CONCLUSION This paper presents a hardware implementation for one of the most powerful stream ciphers, that is known as RC4.  ... 
doi:10.21608/asat.2007.24121 fatcat:rqg3cob6ondjlhf75chg4xme2i

Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture

Zong Wang, Tughural Arslan, Ahmet Erdogan
2008 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)  
As our simulation result shows, RC4 stream cipher throughput achieves as high as 60 Mbps with 128 bits key size and 1024 bits data buffer packet.  ...  The implementations target a novel Reconfigurable Instruction Cell Array (RICA) based architecture which has recently been developed [8], with the aim of achieving low power, high performance and programming  ...  Traditional method is to implement RC4 stream cipher algorithm using software on general processor architecture, which is said to be more efficient then hardware approach due to the inherent nature of  ... 
doi:10.1109/delta.2008.100 dblp:conf/delta/WangAE08 fatcat:ykxr77ph4zevbltzm4m4bmggti

Hardware Implementation of High Speed RC4 Algorithm in FPGA

Chandra Mouli.R, K. R. K. Sastry
2013 International Journal of Computer Applications  
This paper presents high speed and an area efficient hardware implementation of the RC4 algorithm.  ...  The RC4 algorithm is implemented in Verilog HDL.  ...  implementation in [3] require 4 clock cycles, RAM-based hardware implementation of RC4 stream ciphers in [4] and [5] takes 3 clock cycles.  ... 
doi:10.5120/14437-2589 fatcat:sxx57np3znexto5padaixgrw2e

An efficient stream cipher for resistive RAM

Joobeom Yun, Ki-Woong Park, Youngjoo Shin, Hee-Dong Kim
2017 IEICE Electronics Express  
In this paper, we studied data encryption candidates for RRAM and conducted several stream ciphers performance experiments for RRAM.  ...  As a consequence, we showed that Trivium is the most suitable stream cipher algorithm for RRAM. Also, we analyzed the experimental results.  ...  Usually a hardware stream cipher shows better performance than a software stream cipher and can be easily implemented in embedded device circuits.  ... 
doi:10.1587/elex.14.20170179 fatcat:2iqunhg3vbedbcntllyludddi4

Image Encription and Decription Based On Aes &Rc4

Naga Suman Arepalli
2012 IOSR Journal of Electronics and Communication Engineering  
Symmetric algorithms are classified as block cipher (AES) and stream ciphers (RC4) algorithms.  ...  In this paper, we compare the AES (block cipher) algorithm with different modes of operation and RC4 (stream cipher) algorithm in terms of CPU time, encryption time, memory utilization and throughput at  ...  It can be efficiently implemented in both software and hardware. II.  ... 
doi:10.9790/2834-0324650 fatcat:eq7petczkbadxb4iq5tci4gtl4

Fast Hardware Implementation of AES-128 Algorithm in Streaming Output Feedback Mode for Real Time Ciphering

Syed Izhar Hussain Zaidi, Samreen Amir Hussain
2017 International Journal of Security and Its Applications  
This shows the effectiveness of the proposed hardware implementation for real-time streaming cipher applications. Figure 3.  ...  Implementation techniques for various blocks of the algorithm have been discussed for achieving the target performance. The implementation is functionally tested on Virtex -6 FPGA.  ...  This hardware implementation can be used for ciphering real-time streams from satellites, wireless internet modems, 3G/4G mobile GSM networks and other telemetry systems.  ... 
doi:10.14257/ijsia.2017.11.10.04 fatcat:dbh4b2xadncapmmepubrrpizoe

Designing integrated accelerator for stream ciphers with structural similarities

Sourav Sen Gupta, Anupam Chattopadhyay, Ayesha Khalid
2012 Cryptography and Communications  
We propose HiPAcc-LTE, a high performance integrated design that combines the two ciphers in hardware, based on their structural similarities.  ...  As our second case study, we present IntAcc-RCHC, an integrated accelerator for the stream ciphers RC4 and HC-128.  ...  As practical case studies of our proposal, we present HiPAcc-LTE, an integrated high performance hardware accelerator for 3GPP LTE stream ciphers SNOW 3G and ZUC, and IntAcc-RCHC, an integrated accelerator  ... 
doi:10.1007/s12095-012-0074-6 fatcat:vapjaw7vbnbvnc22uideavxrca

Fpga Implementation of Image Encryption and Decryption Using Aes Algorithm Along With Key Encryption

Parul Rajoriya, Nilesh Mohota (Professor)
2017 IOSR Journal of Electronics and Communication Engineering  
A proposed FPGA-based implementation of the Advanced Encryption Standard(AES) algorithm along with key encryption for images is presented in this paper.  ...  This gives low complexity architecture and easily achieves low latency as well as high throughput.  ...  Stream ciphers are further classified as synchronous and self-synchronous stream ciphers.Different synchronous stream ciphers available in the literature are RC4, E0 (a stream cipher used in Bluetooth)  ... 
doi:10.9790/2834-1203024050 fatcat:6jq6saj4cvb2bfxsjwn2gg6kpq

RC4-2S: RC4 Stream Cipher with Two State Tables [chapter]

Maytham M. Hammood, Kenji Yoshigoe, Ali M. Sagheer
2013 Lecture Notes in Electrical Engineering  
We propose RC4 stream cipher with two state tables (RC4-2S) as an enhancement to RC4.  ...  One of the most important symmetric cryptographic algorithms is Rivest Cipher 4 (RC4) stream cipher which can be applied to many security applications in real time security.  ...  There are a number of stream cipher algorithms presented to implement high performance software including IDEA, ORYX, LEVIATHAN, MUGI, RC4, Helix, SEAL, SOBER, and SNOW.  ... 
doi:10.1007/978-94-007-6996-0_2 fatcat:suh4eixqt5fqdoh3rbf6nd37z4

Hardware Implementation Of The Improved Wep And Rc4 Encryption Algorithms For Wireless Terminals

Panu Hamalainen, Marko Hcinnikciinen, Timo Hamalainen, Jukka Saarinen
2015 Zenodo  
RC4 IMPLEMENTATION RC4 is a stream cipher, which means that it operates plaintext a single byte at a time. The high level structure of RC4 is shown in Figure 5 .  ...  Despite its name the cipher is considerably different from Wired Equivalent Privacy (WEP) algorithm included into IEEE 802.11 standard for WLANs [3] . The WEP standard utilizes RC4 stream cipher.  ... 
doi:10.5281/zenodo.37416 fatcat:v357r4ve4rhitae4vjyo55dtcm

Parc4-I: Parallel Implementation of Enhanced RC4A Using Pascs and Loop Unrolling Mechanism

Disha Handa, Bhanu Kapoor
2015 Computer Applications An International Journal  
This paper introduces a parallel approach to symmetric stream cipher security algorithm known as RC4A, which is one of the strong variants of RC4.  ...  Further, with the help of Parallel Additive Stream Cipher Structure and loop unrolling method, encryption/decryption is being done on multi core machine.  ...  The paper proposes the fastest hardware implementation for RC4 cipher and this is achieved by combining two key facts one is hardware pipeline and another is loop unrolling.  ... 
doi:10.5121/caij.2015.2203 fatcat:ygndmhm5l5airiznubw655b4qm
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