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Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring
2018
Sensors
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The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K-500 K temperature range while consuming only 30 µW ...
This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. ...
Acknowledgments: This work was supported by the Sarah and Moshe Zisapel nano-electronics Center at the Technion-Israel Institute of Technology. ...
doi:10.3390/s18051629
pmid:29783742
pmcid:PMC5982330
fatcat:f53ok6cq3jhbpkccsisg5nrrha
Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs
2009
Journal of Integrated Circuits and Systems
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This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures ...
The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime ...
However, one important issue for the PD-SOI CMOS is the large drop in threshold voltage at high drain biases due to the floating body effect (FBE) [8] . ...
doi:10.29292/jics.v4i2.299
fatcat:ocqryihozzgqzgqa4cy5os6fau
A Theoretical Study of Low Power Soi Technology
2013
IOSR Journal of VLSI and Signal processing
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Such circuits are emerging as prime candidates for development using advanced SOI technology processes. ...
The paper introduces the SOI technology with brief design description and the factors that help in developing low power. ...
This can be a serious disadvantage in precision analog design as well as in low power digital design. In practice, there are several ways to avoid the kink effect in PD SOI. ...
doi:10.9790/4200-0253037
fatcat:losoro7sbnc5pb2jkepyfh7yru
SOI for digital CMOS VLSI: design considerations and advances
1998
Proceedings of the IEEE
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The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues. ...
The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. ...
DIGITAL CMOS LOGIC CIRCUITS We now discuss the specific design issues for digital CMOS logic circuits using SOI technology. ...
doi:10.1109/5.663545
fatcat:6lcb6y72k5hphoahsmutzgytbi
SOI technology for the GHz era
2002
IBM Journal of Research and Development
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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. ...
Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices ...
Circuit design and floating-body effects The key feature of PD SOI is the variability of V BS and V T . ...
doi:10.1147/rd.462.0121
fatcat:jtlzzlgcgjgorimfhcepfuc2hq
A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation
2001
IEEE Journal of Solid-State Circuits
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Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. ...
In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. ...
To make mixed signal design in SOI CMOS a practical proposition, the analog designer requires models which can not only handle the special physics of this technology, but which also satisfy more stringent ...
doi:10.1109/4.896235
fatcat:45vbacsdafdqlnbamb4yw3gaam
A Device Design Methodology for Sub-100-nm SOC Applications Using Bulk and SOI MOSFETs
2004
IEEE Transactions on Electron Devices
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The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. ...
While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling ...
design lagging behind the digital by more than two technology generations, there are no definite guidelines for analog SOI MOSFETs. ...
doi:10.1109/ted.2004.829872
fatcat:3kwwcnjkebc7fnwzfpzwx7hybq
The impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures
2021
IEEE Journal of the Electron Devices Society
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different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and 1μm-Silicon-On-Insulator, SOI) and in a wide range of high-temperatures (from 300K to 573K ...
.) that LCE and PAMDLE effects tend to be similar for CMOS ICs technological nodes used and the different high temperatures. ...
The key figures of merit of a MOSFET given in the literature for the design of analog integrated circuits are I DS_SAT , gm and g D in saturation regime. ...
doi:10.1109/jeds.2021.3071399
fatcat:civ75in265a5hlam3dcilz4izi
An SOI thermal-diffusivity-based temperature sensor with ±0.6°C (3σ) untrimmed inaccuracy from −70°C to 225°C
2012
Sensors and Actuators A-Physical
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This work presents the first thermal-diffusivity-based temperature sensor realized in SOI technology; it has an untrimmed inaccuracy of ±0.6 • C (3 ) from −70 • C up to 225 • C and uses up to 7× less power ...
The sensor uses the phase shift of an Electrothermal Filter (ETF) as a proxy for the thermal diffusivity of silicon, D, which has a well-defined 1/T 1.8 temperature dependence. ...
Wim van der Vlist at Delft University of Technology is acknowledged for packaging support. ...
doi:10.1016/j.sna.2012.02.024
fatcat:t3joliwopvgsxnl4pzvkyxrmp4
Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics
2010
Transactions on Electrical and Electronic Materials
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FD SOI transistors have superior advantages over PD SOI transistors in terms of extremely low sub-threshold swing (<65 mV/decade), no floating-body effects, and low threshold voltage variation with temperature ...
reverse-biased pnjunction diode in the off-state MOSFET. ...
doi:10.4313/teem.2010.11.3.093
fatcat:rgsgr2remfbfhaiz4xzelisbf4
Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits
2022
IEEE Journal of the Electron Devices Society
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INDEX TERMS RF CMOS, silicon-on-insulator (SOI) technology, fully depleted (FD) SOI transistor, RF and millimeter-wave performance, high temperature, cryogenic temperature, RF switches, LNA, siliconbased ...
Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic ...
Babak Kazemi Esfeh, Lucas Nyssens, Massinissa Nabet for their overall research contributions to the study of RF-SOI substrates and circuit modules. A warm thanks to Dr. ...
doi:10.1109/jeds.2022.3165877
fatcat:gftbl4l2q5dt5clse4bo7x4swa
PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs
[chapter]
2010
Compact Modeling
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Introduction Compact models of SOI devices provide a bridge between the manufacturing process and circuit design. ...
CMOS SOI applications. ...
The floating body effect in a PD-SOI MOSFET is manifested by the "kinks" in output characteristics at high drain biases. ...
doi:10.1007/978-90-481-8614-3_2
fatcat:7767xeknnzb5lpmo3dsn3yoeya
ZTC bias point of advanced fin based device: The importance and exploration
2015
Facta universitatis - series Electronics and Energetics
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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. ...
The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25 0 C to 225 0 C is reviewed to extend the benchmark of device ...
The inflection point for I D and g m are two important FOM in analog circuit design for both high and low temperature applications. ...
doi:10.2298/fuee1503393m
fatcat:bcgknussebc7vaivevklysoyeq
Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited]
2018
Optics Express
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We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. ...
In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. ...
The authors would also like to thank the Trusted Foundries, MOSIS and the IBM/GlobalFoudries staff involved in handling the design submissions. ...
doi:10.1364/oe.26.013106
pmid:29801342
fatcat:5oiizugzsrdn3cvq63n2bhjwr4
Nanoscale CMOS
1999
Proceedings of the IEEE
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low-power circuit design. ...
His recent work includes the modeling of innovative silicon devices, analysis of CMOS scaling issues, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and ...
ACKNOWLEDGMENT The authors would like to acknowledge the contributions of the Silicon Innovation Laboratory for fabricating the devices described in this paper. ...
doi:10.1109/5.752515
fatcat:siz3jry7hjctlkjesyr5s6vh2m
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