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An Efficient Fault Simulator for QDI Asynchronous Circuits

Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Masoud Zamani, Siamak Mohammadi, Hossein Pedram
2008 2008 4th Southern Conference on Programmable Logic  
So test frameworks such as fault simulator for synchronous circuits are not applicable for asynchronous circuits.  ...  In this paper we present an efficient fault simulator for template-based asynchronous circuits which is based on checking sequence of signals in templates.  ...  It synthesizes high-level description of circuit to pre-designed PCFB and PCHB templates [5] , which produces high speed micro-pipeline.  ... 
doi:10.1109/spl.2008.4547739 fatcat:23pdeq6z2vganmkxqx5xyqsnxe

High-level fault simulation methodology for QDI template-based asynchronous circuits

Behnam Ghavami, Alireza Tajary, Hamid-Reza Zarandi
2009 TENCON 2009 - 2009 IEEE Region 10 Conference  
This categorization is used to introducing a new high level fault simulation methodology for these circuits.  ...  In this paper we study transistor-level single stuck-at faults in traditional asynchronous templates and categorize their effects on the functionality of circuit.  ...  In this paper we present an efficient high-level fault simulation strategy for template-based QDI asynchronous circuits.  ... 
doi:10.1109/tencon.2009.5395804 fatcat:nji65jzatvgmvinpkhu2gv6bn4

Fault tolerant clockless wave pipeline design

T. Feng, B. Jin, J. Wang, N. Park, Y. B. Kim, F. Lombardi
2004 Proceedings of the first conference on computing frontiers on Computing frontiers - CF'04  
Electronic noise may devastate the operational confidence level of the clockless wave pipeline.  ...  The specific architectural model investigated in this paper is the two-phase clockless asynchronous wave pipeline [10] which is ideally supposed to yield the theoretical maximum of performance.  ...  The fault models for asynchronous wave pipeline has been established and proposed in [15] . The fault models were based on the target architecture of the two-phase asynchronous wave-pipelines.  ... 
doi:10.1145/977091.977142 dblp:conf/cf/FengJWPKL04 fatcat:t7zxyfflkvcqbbfbceqgtxukzu

Data-feedthrough faults in circuits using unclocked storage elements

W.K. Al-Assadi, A.P. Jayasumana, Y.K. Malaiya, C.Q. Tong, D. Lu
1994 Electronics Letters  
The authors investigate the implications of such faults on the behaviour of circuits using unclocked SEs.  ...  It is shown that effects of data-feedthrough faults at the behavioural level are different from those due to stuck-at faults, and therefore tests generated for the latter may be inadequate.  ...  The enhanced fault model proposed for such SEs shows high explicit fault coverage compared with the stuck-at model.  ... 
doi:10.1049/el:19940514 fatcat:tpxuztyibvcsfchtxb2dc4jo74

Fault detection and isolation techniques for quasi delay-insensitive circuits

C. LaFrieda, R. Manohar
2004 International Conference on Dependable Systems and Networks, 2004  
The combination of these is an asynchronous defect-tolerant circuit where a large class of faults are tolerated, and the remaining faults can be both detected easily and isolated to a small region of the  ...  The asynchronous nature of quasi delay-insensitive circuits combined with layout techniques makes the design tolerant to delay faults.  ...  We begin with an overview of both our gate model, QDI circuits, and fault model (Section 2).  ... 
doi:10.1109/dsn.2004.1311875 dblp:conf/dsn/LaFriedaM04 fatcat:i7sdhgjzwfhf3cvzlou5vqg5gm

Testing delay faults in asynchronous handshake circuits

Feng Shi, Yiorgos Makris
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of gate delays.  ...  Therefore, any delay fault in the circuit may cause one of two problems, namely performance degradation or logic errors.  ...  HANDSHAKE CIRCUITS As one of the most established design styles of asynchronous circuits, handshake circuits have a fully automated design flow from the high-level behavioral description to the physical  ... 
doi:10.1145/1233501.1233540 dblp:conf/iccad/ShiM06 fatcat:5xosrlpu7rbifjsa2dnioqzzvy

Testing Delay Faults in Asynchronous Handshake Circuits

Feng Shi, Yiorgos Makris
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of gate delays.  ...  Therefore, any delay fault in the circuit may cause one of two problems, namely performance degradation or logic errors.  ...  HANDSHAKE CIRCUITS As one of the most established design styles of asynchronous circuits, handshake circuits have a fully automated design flow from the high-level behavioral description to the physical  ... 
doi:10.1109/iccad.2006.320085 fatcat:ve3wse4xyzd4bgeaqh6w4okife

An EDA tool for implementation of low power and secure crypto-chips

Behnam Ghavami, Hossein Pedram, Mehrdad Najibi
2009 Computers & electrical engineering  
We suggest a restructuring on the conditional statements in the high-level description of the circuit which leads to a considerable optimization in power consumption after the decomposition of the system  ...  In the proposed flow, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits  ...  Additional error detection based on other high level fault-tolerant methods can be added easily due to the specification of the circuit.  ... 
doi:10.1016/j.compeleceng.2008.06.014 fatcat:3bjrexmnbvbilme54efiw64hni

Asynchronous Design—Part 2: Systems and Methodologies

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of  ...  h THIS TWO-PART article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art.  ...  Acknowledgment The authors appreciate the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606, and OCI-1127361.  ... 
doi:10.1109/mdat.2015.2413757 fatcat:bpxnljdkofh6ppyovk6sp4pknm

Partial-scan delay fault testing of asynchronous circuits

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, A. Taubin
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.  ...  Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial.  ...  Circuits from the second class are known to have high stuck-at testability. We expected that a high level of path delay fault testability could be achieved with a low scan ratio.  ... 
doi:10.1109/43.736191 fatcat:vn6vggv4bzhrfd4tg7ukotbm7y

Partial scan delay fault testing of asynchronous circuits

Kishinevsky, Kondratyev, Lavagno, Saldanha, Taubin
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.  ...  Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial.  ...  Circuits from the second class are known to have high stuck-at testability. We expected that a high level of path delay fault testability could be achieved with a low scan ratio.  ... 
doi:10.1109/iccad.1997.643619 dblp:conf/iccad/KishinevskyKLST97 fatcat:3ql5btxqcvahje2pgfryyleoh4

Asynchronous circuits transient faults sensitivity evaluation

Y. Monnet, M. Renaudin, R. Leveugle
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).  ...  Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults.  ...  Fault models were defined in the context of asynchronous circuits. Consequences of the propagation of a transient fault were identified and examined at the behavioral level.  ... 
doi:10.1145/1065579.1065805 dblp:conf/dac/MonnetRL05 fatcat:lo2gnqd7pbd7fozifwtpyxrqfa

Asynchronous circuits transient faults sensitivity evaluation

Y. Monnet, M. Renaudin, R. Leveugle
2005 Proceedings. 42nd Design Automation Conference, 2005.  
The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).  ...  Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults.  ...  Fault models were defined in the context of asynchronous circuits. Consequences of the propagation of a transient fault were identified and examined at the behavioral level.  ... 
doi:10.1109/dac.2005.193936 fatcat:53sx44txdjgkhks7vgeqf5llca

Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design

Tao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park
2010 IEEE Transactions on Instrumentation and Measurement  
A clockless-induced datawave fault model is proposed for clockless fault-tolerant design.  ...  The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous  ...  The propagation of the datawave within a pipelined circuit is intermittent. Once the datawave enters the circuit, it is assigned a request signal, at either high or low level.  ... 
doi:10.1109/tim.2009.2030917 fatcat:frrcdew6sbfszmxxfghinvopyq

Deductive Fault Simulation for Asynchronous Sequential Circuits

Roland Dobai, Elena Gramatova
2009 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools  
Other classes of asynchronous circuits can be represented under this model Shi et al.: Test Generation for Ultra-High-Speed Asynchronous Introduction About this work Developed and implemented a deductive  ...  Introduction Classes of the asynchronous circuits Asynchronous circuits can be classified at the gate level as self-timed, speed-independent, delay-insensitive, quasi-delay-insensitive.  ...  Advantage The simulation of fault-free and faulty circuit can be done in the same way.  ... 
doi:10.1109/dsd.2009.129 dblp:conf/dsd/DobaiG09 fatcat:d5mkl3hsivg6bcpgtepzinvrre
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