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High-Performance Embedded Architecture and Compilation Roadmap
[chapter]
2007
Lecture Notes in Computer Science
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-it can even serve as an introduction to scientists and professionals interested in learning about high-performance embedded architecture and compilation. ...
One of the key deliverables of the EU HiPEAC FP6 Network of Excellence is a roadmap on high-performance embedded architecture and compilation -the HiPEAC Roadmap for short. ...
Furthermore it is a roadmap on highperformance embedded architecture and compilation, hence it is about future embedded hardware and tools to exploit that hardware in the broad sense. ...
doi:10.1007/978-3-540-71528-3_2
fatcat:ywmebvj7wrfb3ojghsjs4w3fy4
Foreword
2015
International Conference on High Performance Embedded Architectures and Compilers
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We hope this workshop will lead to new insights and fruitful discussions around its relatively novel topic within the context of High Performance Computing. Munich, December 2015 ...
Out of these, the programme committee selected six high quality papers for publication. In the process, each paper received three reviews. ...
Workshop Description The task of a high performance computing system is to carry out its calculations (mainly scientific applications) with maximum performance and energy efficiency. ...
doi:10.14459/2016md1286947
dblp:conf/hipeac/TrinitisW16
fatcat:viq6v5e4rvhgjdnoxcb6zd7xqi
Modeling Information Routing With Noninterference
2016
International Conference on High Performance Embedded Architectures and Compilers
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To achieve the highest levels of assurance, systems based on the MILS architecture need to be formally analysed. ...
As an illustration of our approach, we formally model and analyze an example system inspired by the GWV Firewall. ...
Formalizing a verification framework that takes into account the full tenets of information theory, probability theory, cryptography, and related subjects remains a daunting task, and tools for performing ...
doi:10.5281/zenodo.47980
dblp:conf/hipeac/KoolenS16
fatcat:nanskixuezeuxlowxctw4pot2q
Cybersecurity In The Railway Sector
2018
International Conference on High Performance Embedded Architectures and Compilers
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While these developments bring many advantages for the industry and its users, they also present new opportunities for cyber-criminals and terrorists. ...
The CYRail project is identifying not only the IT security risks, but also appropriate methods for addressing them, including specifications and recommendations for secure modern rail systems design and ...
One approach is to build a MILS architecture that enables separation and isolation of systems and components. ...
doi:10.5281/zenodo.1306072
dblp:conf/hipeac/EngqvistP18
fatcat:jhccpduhsjd3bdsrdauztmc2fa
Mils Initiatives Within The Open Group
2015
International Conference on High Performance Embedded Architectures and Compilers
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Design a Policy Architecture § Abstract architecture diagram represented by "boxes and arrows" § Operational components and architecture achieve system purpose § Assumes architecture (components and ...
MILS Initiatives
21
20 January 2015
MILS
System
Claims
Sub-case
Sub-case
Sub-case
Policy Architecture
Environment
MILS System High-Level
Assurance Argument
MP
Claims
P A
Claims ...
Evaluation and Certification Support ...
doi:10.5281/zenodo.47988
dblp:conf/hipeac/DeLong15
fatcat:2fsy6dc4v5eppcgksitrgmmpzy
Applying Mils To Multicore Avionics Systems
2016
International Conference on High Performance Embedded Architectures and Compilers
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In this paper, the potential requirements for the implementation of a separation kernel to support MILS systems on multicore processor architectures will be considered, and the design challenges associated ...
The implementation of the Multiple Independent Levels of Security (MILS) software architecture on modern microprocessor architectures has become technically feasible in recent years. ...
This paper is protected and subject to copyright law. The author and Wind River Systems, Inc. ...
doi:10.5281/zenodo.47978
dblp:conf/hipeac/Parkinson16
fatcat:g53mopdbl5cqrgrqxuklokcyzq
An Architecture-Centric Process For Mils Development
2016
International Conference on High Performance Embedded Architectures and Compilers
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This would leverage architecture models and augment them with security information in order to perform the different activities of the development process, including security policy validation, implementation ...
Safety-critical embedded systems are now software-reliant and evolving at an incredible pace. ...
Architecture Specification The AADL [14] has been used for design and validation of safetycritical systems from different perspectives, such as performance [5] or safety [4] . ...
doi:10.5281/zenodo.47976
dblp:conf/hipeac/DelangeNFK16
fatcat:jrcqtj3khzal7nbd543mpvolqy
DDM-VMc
2011
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers - HiPEAC '11
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We present the architecture of DDM-VM c and provide an in-depth performance analysis using a suite of standard computational benchmarks. ...
The evaluation shows that DDM-VMc scales well and tolerates scheduling overheads and memory latencies effectively. ...
DDM-VM c targets a high-performance heterogeneous multi-core system that requires the programmer to handle many low-level details, such as memory management and synchronization tasks. ...
doi:10.1145/1944862.1944869
dblp:conf/hipeac/ArandiE11
fatcat:5nmnul7jkvbzjlhi6yvyo7ivw4
Provencore: Towards A Verified Isolation Micro-Kernel
2015
International Conference on High Performance Embedded Architectures and Compilers
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The Smart models are used to generate efficient C code and express low- and high-level properties of the implementation, and first among them guarantees of integrity and confidentiality for the various ...
This operating system is both developed and specified in a single specification language called Smart. ...
In a similar way, compilers are key components because they bridge the gap between the sources and the actual executable binaries. ...
doi:10.5281/zenodo.47990
dblp:conf/hipeac/Lescuyer15
fatcat:lvlur2a3y5aqjh4dmqwyseltjm
Classic And Adaptive Autosar In Mils Terms
2018
International Conference on High Performance Embedded Architectures and Compilers
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focus on runnables that are compiled together, and we will highlight the difference as well as the evolution of AUTOSAR Adaptive that is much closer to the avionic model. ...
We map the AUTOSAR standards to MILS, to learn about (1) how well MILS systems can be used for AUTOSAR and vice-versa and (2) what other aspects the communities could mutually learn from. ...
Acknowledgment This work has received partial funding from the European Union's Horizon H2020 research and innovation program under grant agreement No 731456 (certMILS, https://certmils.eu/). ...
doi:10.5281/zenodo.1307651
dblp:conf/hipeac/BlasumT18
fatcat:wg4dtyuzafht7edxuakyxinsva
Euro-Mils: Building And Certifying Modular Secure Systems
2016
International Conference on High Performance Embedded Architectures and Compilers
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Presentation on EURO-MILS building and certifying modular secure systems ...
requires trustworthy ICT
MILS Architecture
-High-assurance security
architecture
-Scalable and affordable
security
-Compositional design,
assurance, security
EURO-MILS: European MILS architecture ...
Components specs, …
MILS Vulnerability
analysis
High-assurance
methods
Formal methods for
components and
system integration
Formal methods in
Common Criteria
MILS
Architecture
Template ...
doi:10.5281/zenodo.47975
dblp:conf/hipeac/Tverdyshev16
fatcat:mfh6lpceubbezequtbesov5ijy
Euro-Mils: Building And Certifying Modular Secure Systems
2015
International Conference on High Performance Embedded Architectures and Compilers
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EURO-MILS presentation on building and certifying modular secure systems ...
and using unidirectional flow)
T --composition
Low--criticality App High--criticality App
MILS Platform (Separation Kernel)
Hardware (CPUs, memory, and devices)
MILS Architecture Network Actuator ...
Components specs, …
MILS Vulnerability
analysis
High--assurance
methods
Formal methods for
components and
system integration
Formal methods in
Common Criteria
MILS
Architecture
Template ...
doi:10.5281/zenodo.47972
dblp:conf/hipeac/Tverdyshev15
fatcat:utacckg62jeobe6lpkzllamer4
Mils Compliant Software Architecture For Satellites
2016
International Conference on High Performance Embedded Architectures and Compilers
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In the paper we will describe an architecture and software elements to ensure high level of security on-board a spacecraft. ...
Both boards are physically interconnected by a high speed spacewire (SpW) link. ...
Figure 8 . 8 Routing
• MultiDSP/uProcessor Architecture (MDPA) or SCOC3 processor boards (Airbus OBC products) • On-Board Computer System Architecture (OBC-SA) High Reliable Processing Board based on ...
doi:10.5281/zenodo.47973
dblp:conf/hipeac/HerpelKMESK16
fatcat:oetxwwhn2raefd5zrsb63fa2ua
Extended histories
2011
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers - HiPEAC '11
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In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. ...
In SPEC2000 benchmarks, using all the L2 accesses as history for prefetcher improves the performance in terms of both IPC and misses reduced over techniques that use only primary misses as history. ...
Access Map Prefetch Access map prefetching [7] is a prefetching technique that can overcome the negative side effects -reordering of memory accesses -of compiler and micro-architectural optimizations ...
doi:10.1145/1944862.1944875
dblp:conf/hipeac/ManikantanGR11
fatcat:i75vrtithzculiulzkztpl4hae
TypeCastor
2011
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers - HiPEAC '11
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Dynamic typing is a barrier for JavaScript applications to achieve high performance. ...
Though not developed for pure performance, TypeCastor achieves 5.6% and 12.7% higher scores compared to current Chrome V8 and Mozilla TraceMonkey engines respectively. ...
In the first phase, the high level and sophisticated optimizations are performed with static compilation. ...
doi:10.1145/1944862.1944873
dblp:conf/hipeac/LiCL11
fatcat:42gkhngrprcbfah4mwzihcr3ym
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