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Synthesis of optimized hardware transactors from abstract communication specifications

Dongwook Lee, Hyungman Park, Andreas Gerstlauer
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
In a TLM methodology, communication details are abstracted away to the level of protocol transactions.  ...  Even with transaction-level modeling and high-level synthesis of hardware, communication interfaces still have to be manually designed at a low protocol level.  ...  Starting from an untimed architecture model, we follow a four-step methodology to synthesize communication down to a protocol-level TLM, transform the TLM into a block-level model (BLM), further synthesize  ... 
doi:10.1145/2380445.2380508 dblp:conf/codes/LeePG12 fatcat:m3taxwwyc5at7oxrviossunbza

Hardware/software codesign and rapid prototyping of embedded systems

F. Slomka, M. Dorfel, R. Munzenberger, R. Hofmann
2000 IEEE Design & Test of Computers  
tools for the analysis, synthesis, and rapid prototyping of distributed embedded real-time systems and presents a complete design flow from specification to implementation.  ...  Often, simulation tools are used for exploring the design space and for validating the functional and timing behaviors of embedded systems.  ...  The framework contains standard tools (such as high-level synthesis and a software compiler) for the synthesis of hardware and software modules.  ... 
doi:10.1109/54.844331 fatcat:7wla7cdyifeenb6wwfrwclbkaq

Specify-explore-refine (SER)

A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
With SER at its core, ELEGANT provides a seamless tool chain for modeling verification and synthesis from top-level specification down to embedded HW/SW implementation.  ...  Following a Specify-Explore-Refine methodology, SER supports system-level design space exploration, interactive platform development and automatic model refinement and model generation.  ...  For synthesis of hardware components, ELEGANT includes the CyberWorkBench high-level, C-to-RTL synthesis tool originally developed at NEC [14] .  ... 
doi:10.1145/1391469.1391617 dblp:conf/dac/GerstlauerPSGNAN08 fatcat:pqfqi4vk5zcijgeaukomditlxy

A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs

Florent Berthelot, Fabienne Nouvel, Dominique Houzet
2008 EURASIP Journal on Embedded Systems  
Figure 5 depicts the overall methodology flow. Each macrocode is translated toward a high-level language (HDL or C/C++) for each HW and SW component.  ...  To address these issues, this work uses the SynDEx CAD tool for the high-level steps of our methodology, which include automatic design partitioning/scheduling and RTL code generation for FPGA.  ... 
doi:10.1155/2008/793919 fatcat:con7yeic5jftrhyp54vdvneoyi

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Abdelhakim Alali, Hasna Elmaaradi, Mohammed Khaldoun, Mohamed Sadik
2021 Indonesian Journal of Electrical Engineering and Informatics (IJEEI)  
The objective of this article is to analyze each tool at several levels and to discuss the benefit of each in the scientific community.  ...  electronic system, from its modeling to its physical implementation.  ...  OpenCL [29] is a platform developed in C and C++ that aims at the high-level synthesis of models with more speed while decreasing the Time to Market.  ... 
doi:10.52549/ijeei.v9i4.3243 fatcat:k76nmwodi5cfxk4c4hk3nojc7e

A Novel Automate Python Edge-to-Edge: From Automated Generation on Cloud to User Application Deployment on Edge of Deep Neural Networks for Low Power IoT Systems FPGA-Based Acceleration

Tarek Belabed, Vitor Ramos Gomes da Silva, Alexandre Quenon, Carlos Valderamma, Chokri Souani
2021 Sensors  
Based on a high-level Python interface that mimics the leading Deep Learning software frameworks, it offers an easy way to implement a hardware-accelerated DNN on an FPGA.  ...  the necessary binaries for both FPGA and software parts, and (c) deployment: the SoC on the Edge receives the resulting files serving to program the FPGA and related Python libraries for user applications  ...  Pseudo-code for the C/C++ template used for a DNN layer.  ... 
doi:10.3390/s21186050 pmid:34577258 pmcid:PMC8467982 fatcat:4tighgu2cnejnfa7cn2xxiu3by

Data-aware process networks

Christophe Alias, Alexandru Plesco
2021 Proceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction  
With the emergence of reconfigurable FPGA circuits as a credible alternative to GPUs for HPC acceleration, new compilation paradigms are required to map high-level algorithmic descriptions to a circuit  ...  We outline our compilation algorithms to map a C program to a DPN (front-end), then to map a DPN to an FPGA configuration (back-end).  ...  In particular, we show that regular process networks induces a general compilation methodology, and we show how to instanciate it on the DPN case to compile an FPGA circuit configuration from a C-level  ... 
doi:10.1145/3446804.3446847 fatcat:pyhil53nuzg2hk2dc7pbj7zh6q

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

Rafał Kiełbik, Kamil Rudnicki, Zbigniew Mudza, Jarosław Jung
2020 Electronics  
Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead.  ...  This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification.  ...  The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.  ... 
doi:10.3390/electronics9091482 fatcat:sx2xl6fcxzflvfplpds7om6tla

Improving the performance of message parsers for embedded systems

Jigar Solanki, Laurent Réveillère, Yérom-David Bromberg, Bertrand Le Gal, Tégawendé F. Bissyandé
2013 Proceedings of the 28th Annual ACM Symposium on Applied Computing - SAC '13  
To validate our approach, we have used Zebra to generate hardware parsers for widely used protocols, namely HTTP, SMTP, SIP, and RTSP.  ...  Unfortunately, developing such parsers is a daunting task for most developers as it is at the crossroads of several areas of expertise, such as low-level network programming, or hardware design.  ...  From a high level specification, used to describe text-based protocol message formats and related processing constraints, a compiler generates both HDL synthesisable specification to be plugged in a hardware  ... 
doi:10.1145/2480362.2480643 dblp:conf/sac/SolankiRBGB13 fatcat:vvg6ato7ubh6xf63nxnqkudfzi

A Flexible SoC and Its Methodology for Parser-Based Applications

Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki
2016 ACM Transactions on Reconfigurable Technology and Systems  
This partial reconfiguration is performed using a dedicated hardware component (ICAP resource for Xilinx FPGA) and a specific synthesis methodology.  ...  To achieve the evaluation of the aforementioned tools, parsers' C source codes were generated from high level protocol specifications.  ...  ELECTRONIC APPENDIX The electronic appendix for this article can be accessed in the ACM Digital Library. Received March 2014; revised July 2014; accepted -  ... 
doi:10.1145/2939379 fatcat:fikk5qyt3jehrodhs4zgptggbq

Software-defined Radios: Architecture, State-of-the-art, and Challenges [article]

Rami Akeela, Behnam Dezfouli
2018 arXiv   pre-print
SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks.  ...  Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware.  ...  In [167] , the authors introduce a method based on RS-422 serial communication and High Level Data Link Control (HDLC) protocol to update DSP and FPGA systems.  ... 
arXiv:1804.06564v1 fatcat:ogkut4aibnfarbrvjkihdfiqnu

The Environment for Mapping SystemC Multi-module Specifications onto NoC Architectures

Stanislaw Deniziak, Robert Tomaszewski
2008 Open Cybernetics and Systemics Journal  
This work presents a methodology for mapping of a SystemC specification onto a given Network-on-Chip (NoC) architecture, for the purpose of FPGA prototyping.  ...  For each module implemented in hardware a VHDL code of the NI is generated. NIs convert transmitted data into/from network packets according to the communication protocol.  ...  In [18] graph models are used for communication synthesis. A method of mapping system level task graph onto optimal NoC with a mesh topology is presented in [3] .  ... 
doi:10.2174/1874110x00802010142 fatcat:6vnvjofaefc3paiaxp3tgwfwmq

Performance Analysis of AODV Routing for Wireless Sensor Network in FPGA Hardware

Namit Gupta, Kunwar Singh Vaisla, Arpit Jain, Adesh Kumar, Rajeev Kumar
2022 Computer systems science and engineering  
Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task.  ...  The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated  ...  The Virtex-5 FPGA isused for the same. The main steps for FPGA synthesis are logic placement, routing and implementation to burn the bit file in FPGA.  ... 
doi:10.32604/csse.2022.019911 fatcat:hiifzs6vk5dkvngwauuulie3p4

System simulation and optimization using reconfigurable hardware

Martin Lukasiewycz, Shanker Shreejith, Suhaib A. Fahmy
2014 2014 International Symposium on Integrated Circuits (ISIC)  
This paper presents a methodology for simulating and automatically optimizing distributed cyber-physical systems using reconfigurable hardware.  ...  onto an FPGA are presented. (2) An optimization model is proposed that encodes the topology, task distribution, and communication in a very efficient representation.  ...  We have also designed high level software Application Programming Interfaces (APIs) to communicate with these interfaces from a workstation.  ... 
doi:10.1109/isicir.2014.7029545 dblp:conf/isicir/LukasiewyczSF14 fatcat:omy5jlk5j5gq3kc6f5d5z4g3m4

An OpenCores/Opensource based Embedded System-on-Chip Platform for Voice over Internet Protocol [chapter]

Sabrina Titri, Nouma Izeboudjen, Fatiha Louiz, Mohamed Bakiri, Faroudja Abid, Dalila Lazib, Leila Sahli
2011 VoIP Technologies  
To test the embedded network emulation, the Ethernet IP core is chosen as a network controller. The Ethernet frame from Ethreal is used to test the network application between FPGA board and PC.  ...  By using the Make language, a Makefile is created for simulation and another one for synthesis.  ...  While VoIP is undoubtedly a powerful and innovative communication tool for everyone, voice communication over the Internet is inherently less reliable than the public switched telephone network, because  ... 
doi:10.5772/13385 fatcat:y7x6f46uunhqnfgpe7gm6ya3yy
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