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A Comparative Analysis of Performance of Shared Memory Cluster Computing Interconnection Systems
2014
Journal of Computer Networks and Communications
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In this paper, a detailed comparative study on four important and different classes of shared memory cluster architectures has been made. ...
The systems taken up for the purpose of the study are shared memory clusters, hierarchical shared memory clusters, distributed shared memory clusters, and the virtual distributed shared memory clusters ...
Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper.
Journal of Computer Networks and Communications ...
doi:10.1155/2014/128438
fatcat:qcjwpzai3bewnnvkti7s6vu7tq
Retrospective: the Cedar system
1998
25 years of the international symposia on Computer architecture (selected papers) - ISCA '98
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Another goal was to have the prototype "achieve Cray-1 speeds for programs written in high-level languages and automatically restructured" by a compiler. ...
accepted as a way to speed up the execution of a single program. ...
File systems in each cluster were made available to the user as a single abstraction. ...
doi:10.1145/285930.285965
dblp:conf/isca/VeidenbaumYKPPDG98
fatcat:obv6ipwmffbh7e27pzrhkzaza4
A Hierarchical Shared Memory Cluster Architecture with Load Balancing and Fault Tolerance
2011
International Journal of Computer Applications
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Recently a great deal of attention has been paid to the design of hierarchical shared memory cluster system. ...
The hierarchical load balancing approach focuses on reducing the redistribution cost. The fault tolerant model is adopted to build highly available clusters in hierarchical shared memory clusters. ...
hierarchy. iii) Cluster shared memory (Ms 1 ) globally shared by processors in each cluster at the 1st level of hierarchy. ...
doi:10.5120/3038-4121
fatcat:ad5ngyzz7be3dmn42t67iqorhi
Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing
2014
2014 IEEE Computer Society Annual Symposium on VLSI
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Moreover, our platform architecture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing ...
In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. ...
Our results for machine learning algorithms have demonstrated that our solution allows to significantly reduce the data memory access conflicts even for a high number of cores in the cluster. ...
doi:10.1109/isvlsi.2014.77
dblp:conf/isvlsi/KanounRAS14
fatcat:vu3tpx4wffa6fc5kiteuf6gnxa
What's Up with the Storage Hierarchy?
2017
Conference on Innovative Data Systems Research
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Today, who can make predictions about the future of the storage hierarchy? Both main memory and storage systems are undergoing profound transformations. ...
The impact of these transformations on the storage hierarchy is unclear. Yet, they raise interesting research questions. ...
On a cluster, the storage hierarchy is stretched across two dimensions (memory/disk, local/rack/cluster) and offers a range of possible trade-offs in terms of latency, bandwidth and capacity [3] . ...
dblp:conf/cidr/Bonnet17
fatcat:ji4pvfutljcpdfncnexv2gjtum
Bridging the Gap Between Cluster and Grid Computing
[chapter]
2006
Lecture Notes in Computer Science
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The Internet computing model with its ubiquitous networking and computing infrastructure is driving a new class of interoperable applications that benefit both from high computing power and multiple Internet ...
Ro c meµ is a platform originally designed to support the operation of multi-SAN clusters that integrates application modeling and resource allocation. ...
Next, we describe the mapping process used to produce the hierarchy presented in figure 5 , which corresponds to the fusion of two hierarchies -the hierarchy that represents the cluster ( figure 4(a) ...
doi:10.1007/11752578_25
fatcat:z7sixbkmovfg5lpcfdbd6chjui
Design and evaluation of a TOP100 Linux Super Cluster system
2004
Concurrency and Computation
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The High Performance Computing Center North (HPC2N) Super Cluster is a truly self-made high-performance Linux cluster with 240 AMD processors in 120 dual nodes, interconnected with a high-bandwidth, low-latency ...
In summary, this $500 000 system is extremely cost-effective and shows the performance one would expect of a large-scale supercomputing system with distributed memory architecture. ...
The procurement of the hardware was made possible by a grant from The Kempe Foundations. ...
doi:10.1002/cpe.787
fatcat:h2ulkmmqendhdfdb3f2eam6sry
Deploying applications in multi-SAN SMP clusters
2009
International Journal of Computational Science and Engineering (IJCSE)
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In this paper we present a novel approach to the exploitation of clusters that allows integrating in a unique metaphor: the representation of physical resources, the modelling of applications and the mapping ...
The proposed abstractions favoured the development of an API that allows combining and benefiting from the shared memory, message passing and global memory paradigms. . ...
Global memory A fundamental issue in cluster computing is memory hierarchy and as a consequence the exploitation of data locality is one of the keys to achieve high-performance. ...
doi:10.1504/ijcse.2009.027376
fatcat:6ff45oddena2bp3axmenp7en4m
Hierarchical Dataflow Model for efficient programming of clustered manycore processors
2017
2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
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Deployment of an image processing application on a many-core MPSoC results in speedups of up to 58.7 compared to the sequential execution. ...
Dataflow Models of Computation (MoCs) are increasingly used for developing parallel applications as their high-level of abstraction eases the automation of mapping, task scheduling and memory allocation ...
High-Level Hierarchy (Inter-Cluster) The high-level mapping of hierarchical actors is more efficient as it is adapted for coarse-grained granularity. ...
doi:10.1109/asap.2017.7995270
dblp:conf/asap/HascoetDND17
fatcat:zrl6ffctonhrzixhzhh35nbzdy
Modeling and Simulative Performance Analysis of SMP and Clustered Computer Architectures
2000
Simulation (San Diego, Calif.)
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Due to the high fidelity of our models, these low-level performance statistics are more practically gathered than in testbed analyses yet more accurate than the results of purely analytical models. ...
Processor, bus, and network models are used to construct and simulate the architectures of symmetric multiprocessors (SMPs), clusters of uniprocessors, and clusters of SMPs. ...
A cluster of SMPs attempts to garner the benefits of locality and cost-effectiveness available in SMPs while also benefiting from the removal of the bottleneck and limits on scalability associated with ...
doi:10.1177/003754970007400203
fatcat:t3aac62snrchdb4yojb5fnuvja
POSTER: Leveraging deep memory hierarchies for data staging in coupled data-intensive simulation workflows
2014
2014 IEEE International Conference on Cluster Computing (CLUSTER)
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However, further research is necessary in order to understand how growing data sizes from data intensive simulations coupled with limited DRAM capacity in High End Computing clusters will impact the effectiveness ...
In this work, we propose using deep memory levels for data staging, utilizing a multi-tiered data staging method with both DRAM and solid state disk (SSD). ...
Furthermore, it ensures that data is moved to DRAM prior to a read request in order to avoid the penalty of reading data from a lower level of the memory hierarchy, i.e., the SSD level, and improving the ...
doi:10.1109/cluster.2014.6968744
dblp:conf/cluster/JinZSBPKKCHCP14
fatcat:z63di74hzzcllgxn3gy6cwvuv4
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy
2007
Parallel Architecture and Compilation Techniques (PACT), Proceedings of the International Conference on
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The levels of memory hierarchy could include on-die storage such as caches, local DRAM, or even remote memory accessed over high-speed interconnect. ...
the memory hierarchy. ...
Stream Scheduling optimizes the use of available memory at each level of the hierarchy by varying a collection of parameters(tunables) in the Sequoia program, used with blocking primitives for task decomposition ...
doi:10.1109/pact.2007.4336233
fatcat:m2s7y4urdjc3niwi2g4e6fwtbe
Memory---Sequoia
2006
Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06
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We present Sequoia, a programming language designed to facilitate the development of memory hierarchy aware parallel programs that remain portable across modern machines featuring different memory hierarchy ...
Sequoia abstractly exposes hierarchical memory in the programming model and provides language mechanisms to describe communication vertically through the machine and to localize computation to particular ...
DRAM, or remote memory accessed over high-speed interconnect. ...
doi:10.1145/1188455.1188543
dblp:conf/sc/FatahalianHKLHPERADH06
fatcat:vvqqskhcqbbopiv2q4ha5yvda4
A catalog of classifying characteristics for massively parallel computers
[chapter]
1994
Lecture Notes in Computer Science
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The hardware model The catalog is based on a generic hardware model (Figure 1 ) that most of today's commercial MP systems seem to follow: a three-stage hierarchy of processing nodes, clusters of nodes ...
In order to facilitate an application-oriented assessment of high-performance massively parallel computing systems, a catalog of about 350 classifying characteristics concerning the architecture and software ...
memory hierarchy. ...
doi:10.1007/3-540-57981-8_102
fatcat:q7twxkwe2jccpbm6tmd2kx5vsa
Exposing the Locality of Heterogeneous Memory Architectures to HPC Applications
2016
Proceedings of the Second International Symposium on Memory Systems - MEMSYS '16
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High-performance computing requires a deep knowledge of the hardware platform to fully exploit its computing power. The performance of data transfer between cores and memory is becoming critical. ...
Its memory locality cannot be properly exposed to user-space applications without a significant rework of the current software stack. ...
Memory Architecture of the KNL From the memory point of view, the main innovation in the Knights Landing processor is the integration of a high-bandwidth memory in the package [18] . ...
doi:10.1145/2989081.2989115
dblp:conf/memsys/Goglin16
fatcat:eev2v2bomzcdri2gnsnfyn3fey
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