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Heap data management for limited local memory (LLM) multi-core processors

Ke Bai, Aviral Shrivastava
2010 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10  
This paper presents a scheme to manage heap data in the local memory present in each core of a limited local memory (LLM) multi-core processor.  ...  While it is possible to manage heap data semi-automatically using software cache, managing heap data of a core through software cache may require changing the code of the other threads.  ...  The authors would also like to thank members of the Compiler Microarchitecture Lab for their valuable critique.  ... 
doi:10.1145/1878961.1879015 dblp:conf/codes/BaiS10 fatcat:sizwmck4b5hcpctitgdyazdpxu

Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures

Ke Bai, Aviral Shrivastava
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
Managing heap data of the tasks executing in the cores of an LLM multi-core is an important problem. This paper presents a fully automated and efficient scheme for heap data management.  ...  Limited Local Memory (LLM) multi-core architectures substitute cache with scratch pad memories (SPM), and therefore have much lower power consumption.  ...  CONCLUSION In this paper, we propose a compilation and runtime system to manage unlimited size of heap data for limited local memory multi-core architectures.  ... 
doi:10.7873/date.2013.130 dblp:conf/date/BaiS13 fatcat:fnozjcbjmrgvbg3pvsta7kjdhq

Stack data management for Limited Local Memory (LLM) multi-core processors

Ke Bai, Aviral Shrivastava, Saleel Kudchadker
2011 ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors  
Limited Local Memory (LLM) architectures are power-efficient, scalable memory multi-core architectures, in which cores have a scratch-pad like local memory that is software controlled.  ...  Stack data management of the cores is an important problem in LLM architecture, and our previous work outlined a promising scheme for that [1] .  ...  ACKNOWLEDGMENT This research was partially funded by grants from National Science Foundation CCF-0916652, IIP-0856090, NSF I/UCRC for Embedded Systems, Microsoft Research, SFAz, Raytheon and Stardust Foundation  ... 
doi:10.1109/asap.2011.6043275 dblp:conf/asap/BaiSK11 fatcat:3nvpwoyh3bb7hf73hinrpcv4na

Vector class on limited local memory (LLM) multi-core processors

Ke Bai, Di Lu, Aviral Shrivastava
2011 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11  
Limited Local Memory (LLM) multi-core architecture is a promising solution for scalable memory hierarchy.  ...  In this paper, we propose and implement a scheme to manage vector class in the local memory present in each core of LLM multi-core architecture.  ...  What is needed is a scheme that can efficiently and intuitively manage the vector data in the local memory of Limited Local Memory (LLM) multi-core architectures.  ... 
doi:10.1145/2038698.2038731 dblp:conf/cases/BaiLS11 fatcat:4n3lcjbzwfgixijuuvwf4pypom

The A* speech recognition system on parallel architectures

Patrick Cardinal, Gilles Boulianne, Pierre Dumouchel
2012 2012 11th International Conference on Information Science, Signal Processing and their Applications (ISSPA)  
The multi-thread implementation of the A* decoder combined with GPU for acoustic computation led to a speed-up factor of 5.2 over its sequential counterpart and an improvement of 5% absolute of the accuracy  ...  In addition to the main CPU, almost every computer is equipped with a Graphics Processors Unit (GPU) which is in essence a specialized parallel processor.  ...  This results in a speed-up of 2.09 over a serialized version on a Core i7 quad (4 cores) processor. The speed-up is limited by the memory architecture.  ... 
doi:10.1109/isspa.2012.6310452 dblp:conf/isspa/CardinalBD12 fatcat:ws63663kqvfodm3anqjhyxev5y

Reconstructing Hardware Transactional Memory for Workload Optimized Systems [chapter]

Kunal Korgaonkar, Prabhat Jain, Deepak Tomar, Kashyap Garimella, Veezhinathan Kamakoti
2011 Lecture Notes in Computer Science  
This creates grand challenges to architectural and system designs, as well as to methods of programming these systems, which form the core theme of APPT 2011.  ...  With the continuity of Moore's law in the multicore era and the emerging cloud computing, parallelism has been pervasively available almost everywhere, from traditional processor pipelines to large-scale  ...  SPM Management in CMP with LLM Features Many studies discuss the local memory management in CELL BE processor, which is a typical model of the LLM architecture.  ... 
doi:10.1007/978-3-642-24151-2_1 fatcat:32cx745cn5cfdm5sbeah6eyiey

Ensuring System Integrity Using Limited Local Memory

Yuki Kinebuchi, Shakeel Butt, Vinod Ganapathy, Liviu Iftode, Tatsuo Nakajima
2011
In this paper, we present a new machine architecture called limited local memory (LLM), which we leverage to set up an alternative tamper-proof execution environment for system integrity monitors.  ...  This architecture leverages recent trends in multicore chip design to equip each processing core with access to a small, private memory area.  ...  LLM extends a typical multi-core machine by adding a privileged processing core (core0). Core0 has exclusive access to a small private memory area (hence the name "limited local memory").  ... 
doi:10.7282/t36113v4 fatcat:6lgjn6gtxvgntdzvqo4iq2vfcy

Zephyr

Aaron J. Elmore, Sudipto Das, Divyakant Agrawal, Amr El Abbadi
2011 Proceedings of the 2011 international conference on Management of data - SIGMOD '11  
Multitenant data infrastructures for large cloud platforms hosting hundreds of thousands of applications face the challenge of serving applications characterized by small data footprint and unpredictable  ...  Zephyr uses phases of ondemand pull and asynchronous push of data, requires minimal synchronization, results no service unavailability and few or no aborted transactions, minimizes the data transfer overhead  ...  Acknowledgments The authors would like to thank Shoji Nishimura, the anonymous reviewers, and our anonymous shepherd for providing useful feedback to improve this paper.  ... 
doi:10.1145/1989323.1989356 dblp:conf/sigmod/ElmoreDAA11 fatcat:zobs6nwru5gjdpa25erovm3ruq

Automatic acquisition of grammatical types for nouns

Núria Bel, Sergio Espeja, Montserrat Marimon
2007 Human Language Technologies 2007: The Conference of the North American Chapter of the Association for Computational Linguistics; Companion Volume, Short Papers on XX - NAACL '07   unpublished
AAAI Workshop on Statistical and Empirical Approaches for SDS.  ...  This paper explores what kind of user simulation model is suitable for developing a training corpus for using Markov Decision Processes (MDPs) to automatically learn dialog strategies.  ...  The authors wish to thank Tomas Singliar for his valuable suggestions, Scott Silliman for his support on building the simulation system, and the anonymous reviewers for their insightful comments.  ... 
doi:10.3115/1614108.1614110 fatcat:dhlagg567jcgnd7qxszkja3trq