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Hardware-optimal test register insertion

A.P. Stroele, H.-J. Wunderlich
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Hence, test scheduling is not required, test control is simplified, and test application time is reduced. Index Terms-BILBO, built-in self-test, CBILBO, test register insertion.  ...  Such a scheme is implemented by test registers, for instance built-in logic block observers (BILBO's) and concurrent BILBO's (CBILBO's), which are inserted into the circuit structure at appropriate places  ...  Test registers are added at the primary inputs and outputs of a circuit, and some additional test hardware is inserted into the circuit.  ... 
doi:10.1109/43.703833 fatcat:54p3ehmx3bd3xptx3g636gsgqq

SoftSig

James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
2008 SIGPLAN notices  
in a variety ways for different uses Other instructions for manipulating SRs • Storing, loading, moving, clearing • Explicit membership tests • Intersection, Union, Member insertionRegistering  ...  edisamb.loc Sig X, Y, Z Test for local conflicts with signature register Window of execution Local Disambiguate Sig Conflict?  ... 
doi:10.1145/1353536.1346300 fatcat:fjegijyrenfh7aoiwum26vqlwm

SoftSig

James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
2008 ACM SIGOPS Operating Systems Review  
in a variety ways for different uses Other instructions for manipulating SRs • Storing, loading, moving, clearing • Explicit membership tests • Intersection, Union, Member insertionRegistering  ...  edisamb.loc Sig X, Y, Z Test for local conflicts with signature register Window of execution Local Disambiguate Sig Conflict?  ... 
doi:10.1145/1353535.1346300 fatcat:stf7yczdfnfvvfls7e6yrvt3ci

SoftSig

James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
2008 Proceedings of the 13th international conference on Architectural support for programming languages and operating systems - ASPLOS XIII  
in a variety ways for different uses Other instructions for manipulating SRs • Storing, loading, moving, clearing • Explicit membership tests • Intersection, Union, Member insertionRegistering  ...  edisamb.loc Sig X, Y, Z Test for local conflicts with signature register Window of execution Local Disambiguate Sig Conflict?  ... 
doi:10.1145/1346281.1346300 dblp:conf/asplos/TuckACT08 fatcat:nt3gdsiu3zcvhjovtrq3gygu3e

Efficient BIST hardware insertion with low test application time for synthesized data paths

Nicola Nicolici, Bashir M. Al-Hashimi
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis.  ...  Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input k-bit comparators are used to check  ...  A different approach based on simultaneous test hardware insertion and test scheduling at RTL is presented in [5] .  ... 
doi:10.1145/307418.307507 fatcat:nt5k77yv4fcazktoibx5h2d4zu

WatchdogLite

Santosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic
2014 Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization - CGO '14  
This division of labor between the compiler and the hardware allows for hardware acceleration while using only preexisting architectural registers.  ...  By leveraging the compiler to identify pointers, perform check elimination, and insert the new instructions, this approach attains performance similar to prior hardware-intensive approaches without adding  ...  The compiler explicitly inserts these instructions, uses preexisting static optimizations to eliminate many checks, and performs in-register metadata propagation by copy elimination and standard register  ... 
doi:10.1145/2581122.2544147 fatcat:tazj5xchtzb2bo532ifucxunme

An area-efficient median filtering IC for image/video applications

P.-W. Hsieh, J.-M. Tsai, C.-Y. Lee
1993 IEEE transactions on consumer electronics  
In hardware design, we first map the algorithm onto a regular P E structure, where each PE consistis of shift register, comparator, and some control gates.  ...  This IC implements a modified delete-and-insert sorting algorithm which is very efficient in running order statistics applications.  ...  In this paper, we present an optimal hardware solution for median search, where the complexity only increases linearly according to the number of input data.  ... 
doi:10.1109/30.234627 fatcat:j5wc2uhsdrfqnfdh4cuonau6ou

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures

Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
We show that our compiler algorithms make a predication-only architecture competitive in performance to one with hardware support for tracking divergence.  ...  We prototype our algorithms in a production compiler and evaluate the tradeoffs between software and hardware divergence management on current GPU silicon.  ...  The compiler can optionally insert a check to test whether the predicate condition is null, meaning that instructions under that predicate condition are unnecessary.  ... 
doi:10.1109/micro.2014.48 dblp:conf/micro/LeeGKSKA14 fatcat:uuvfohef7rdmtbjtgdax6sji7m

Serial fault emulation

Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Berbier, Olivier Lepape
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
A hardware emulator based approach has been developed to perform test evaluation on large sequential circuits (at least tens of thousands of gates).  ...  This approach relies both on the flexibility and on the reconfigurability of hardware emulators based on dedicated reprogrammable circuits.  ...  Fig. 3: Hardware initialization of Registers We propose a hardware technique for initializing the registers into a given state.  ... 
doi:10.1145/240518.240669 dblp:conf/dac/BurgunRFBL96 fatcat:e2lurrwt3ffbxj2lsiz5orka2q

Framework for State-Aware Virtual Hardware Fuzzing

Hang Xu, Ganyu Qin, Junhu Zhu, Zimian Liu, Zhiqiang Liu, Keping Yu
2021 Wireless Communications and Mobile Computing  
Evaluation results demonstrate that the proposed SAVHF framework covers an average of more than 61% of virtual hardware code branches in the 18 hours testing and can improve the average code coverage by  ...  Hardware Fuzzing).  ...  By analyzing the abstract syntax tree of the target virtual hardware, we insert instrumentation at the reference code of the key structure that records the information of the virtual hardware control registers  ... 
doi:10.1155/2021/6698311 fatcat:vxt5qrdcdnfppcp3it46qfdfuu

HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems

Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale
2019 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)  
In this paper we present HATE 1 , a HArdware Trojan Emulation Environment.  ...  One of the threats related to such a supply chain are Hardware Trojan Horses (HWTs), that, in the last years, became a serious issue not only for academy but also for industry.  ...  when dealing with reliability and test.  ... 
doi:10.1109/iolts.2019.8854414 dblp:conf/iolts/BolchiniCMRZN19 fatcat:avhekqzh7bdpbdaob4h7lfcj7y

JIT trace-based verification for high-level synthesis

Liwei Yang, Magzhan Ikram, Swathi Gurumani, Suhaib Fahmy, Deming Chen, Kyle Rupnow
2015 2015 International Conference on Field Programmable Technology (FPT)  
High level synthesis (HLS) tools are increasingly adopted for hardware design as the quality of tools consistently improves.  ...  In this paper, we present a debug framework that uses just-in-time (JIT) traces and automated insertion of verification code into the generated RTL to assist in debugging an HLS tool.  ...  However, the complex CDFG transformations and hardware-oriented optimizations prove difficult to formally verify.  ... 
doi:10.1109/fpt.2015.7393155 dblp:conf/fpt/YangIGFCR15 fatcat:mmb7enm32bfgdbyx75ic5vx2tu

A new built-in TPG method for circuits with random pattern resistant faults

X. Kavousianos, D. Bakalis, D. Nikolos, S. Tragoudas
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Built-in self-test, test pattern generators.  ...  The partition of the inputs of a circuit under test (CUT) into groups of compatible inputs reduces the size of a test pattern generator and the length of the test sequence for built-in self-test (BIST)  ...  In this paper, we propose a new TPG scheme that ensures: 100% fault coverage, low hardware overhead, short test length, and at-speed testing because it does not insert logic between the input flip-flops  ... 
doi:10.1109/tcad.2002.1013898 fatcat:qm6dg3j5prfpjk7zymhjrqohpq

Performance Study of a Compiler/Hardware Approach to Embedded Systems Security [chapter]

Kripashankar Mohan, Bhagirath Narahari, Rahul Simha, Paul Ott, Alok Choudhary, Joseph Zambreno
2005 Lecture Notes in Computer Science  
Secure software is created using a secure compiler that inserts hidden codes into the executable code which are then validated dynamically during execution by a reconfigurable hardware component constructed  ...  While the overall approach has been described in other papers, this paper focuses on security-performance tradeoffs and the effect of using compiler optimizations in such an approach.  ...  in failing the test.  ... 
doi:10.1007/11427995_56 fatcat:44g4vstlhjhrtnd4kzz62f5e4i

X-Stacking - A Method for Reducing Control Data for Output Compaction

Rudrajit Datta, Nur A. Touba
2011 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems  
Results indicate that the overall test compression even with factoring in the additional test vectors is significantly improved with the proposed method.  ...  Output response streams containing X's are fed into circular registers, which stack X's on top of one another.  ...  The hardware that is inserted for the proposed method is generic, and only after the actual scan vectors are known, the length of the circular registers and the number of cycles that it is loaded can be  ... 
doi:10.1109/dft.2011.64 dblp:conf/dft/DattaT11 fatcat:lljy3ah4c5fxzbwrvyus2biylq
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