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Hardware-managed register allocation for embedded processors

Xiaotong Zhuang, Tao Zhang, Santosh Pande
2004 SIGPLAN notices  
In this paper, we therefore propose a hardware managed register allocation scheme to allocate more physical registers at runtime and to utilize them.  ...  + Most modern processors (either embedded or general purpose) contain higher number of physical registers than those exposed in the ISA.  ...  In conclusion, managing physical registers with hardware provides a much better solution than filter cache due to extra information embedded in ISA, and the dynamic hardware management mechanism leading  ... 
doi:10.1145/998300.997191 fatcat:rm2mdlpkvbgufe4ul3tdm7xyfe

Hardware-managed register allocation for embedded processors

Xiaotong Zhuang, Tao Zhang, Santosh Pande
2004 Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04  
In this paper, we therefore propose a hardware managed register allocation scheme to allocate more physical registers at runtime and to utilize them.  ...  + Most modern processors (either embedded or general purpose) contain higher number of physical registers than those exposed in the ISA.  ...  In conclusion, managing physical registers with hardware provides a much better solution than filter cache due to extra information embedded in ISA, and the dynamic hardware management mechanism leading  ... 
doi:10.1145/997163.997191 dblp:conf/lctrts/ZhuangZP04 fatcat:vqt3uhx2avcpriuyuzendnrycq

Reconfigurable and Evolvable Architecture for Autonomous on-board systems

Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou, David McIntyre
2008 2008 IEEE National Aerospace and Electronics Conference  
manager of enahle self-growth and reproduction of the reconfigurahle reconfigurable hardware fabric.  ...  granularity embedded technology.  ...  proposed Layer 2 _ Embedded, by [1] for embedding on-board systems for space applications.  ... 
doi:10.1109/naecon.2008.4806550 fatcat:k5czwvjwkbb2perij7usp7oa5y

A system for coarse grained memory protection in tiny embedded processors

Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
2007 Proceedings - Design Automation Conference  
Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system.  ...  In this paper we propose a system that provides memory protection in tiny embedded processors. 1 .  ...  We believe that hardware software co-design techniques are a promising avenue to explore for creating robust software for tiny embedded processors.  ... 
doi:10.1145/1278480.1278534 dblp:conf/dac/KumarSCKS07 fatcat:7hrjpdqw45grtizl74otasmomq

A System For Coarse Grained Memory Protection In Tiny Embedded Processors

Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
2007 Proceedings - Design Automation Conference  
Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system.  ...  In this paper we propose a system that provides memory protection in tiny embedded processors. 1 .  ...  We believe that hardware software co-design techniques are a promising avenue to explore for creating robust software for tiny embedded processors.  ... 
doi:10.1109/dac.2007.375156 fatcat:k6wpmktltzgnpisap64ghs3tpi

Adaptive Data Placement in an Embedded Multiprocessor Thread Library

P. Stanley-Marbell, K. Lahiri, A. Raghunathan
2006 Proceedings of the Design Automation & Test in Europe Conference  
This has led to the need for programming interfaces that expose the capabilities of the underlying hardware.  ...  In addition, for systems that implement applications consisting of multiple concurrent threads of computation, the optimized management of interthread communication is crucial for realizing high-performance  ...  One challenge in the use of such embedded multiprocessors is the dearth of appropriate programming interfaces for effectively exploiting hardware-level concurrency.  ... 
doi:10.1109/date.2006.244065 dblp:conf/date/Stanley-MarbellLR06 fatcat:qgsjbrfrwzby7h272beokdoboe

Hardware Support for Embedded Java [chapter]

Martin Schoeberl
2011 Distributed, Embedded and Real-time Java Systems  
Interface Hardware Support for Embedded Java Hardware Support for Embedded Java Hardware Support for Embedded Java 7 Hardware Support for Embedded Java Personal communication  ...  The SHAP Java processor [72] contains a memory management unit for hardware assisted garbage collection.  ... 
doi:10.1007/978-1-4419-8158-5_7 fatcat:jnk6dqak3bg67jmyflimvw3i24

Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Hiroaki Inoue, Akihisa Ikeno, Tsuyoshi Abe, Junji Sakai, Masato Edahiro
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems.  ...  Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping.  ...  Traditional embedded processors, including ARM MPCores, generally do not allow mode registers or control registers, such as a pointer register for use with a page table, to be simultaneously restored.  ... 
doi:10.1145/1289816.1289830 dblp:conf/codes/InoueIASE07 fatcat:jkuhqnqaq5csxnbk2bk5jxjpz4

A Multi-Core Processor Platform for Open Embedded Systems [article]

Hiroaki Inoue
2010 arXiv   pre-print
modifications; (2) secure processor partitioning with hardware support, by which Operating Systems (OSs) required for base and open applications are securely executed on separate processors; (3) asymmetric  ...  virtualization, by which many OSs over the number of processors are securely executed under secure processor partitioning; and (4) secure dynamic partitioning, by which the number of processors allocated  ...  For example, a domain context of an ARM processor contains one register bank with eight registers, two register banks with five registers, six register banks with two registers, one current processor status  ... 
arXiv:1006.5572v1 fatcat:wo262ewg5ba5rivkakba5ew5de

Power-Efficient Microkernel of Embedded Operating System on Chip [chapter]

Tianzhou Chen, Wei Hu, Yi Lian
2006 Lecture Notes in Computer Science  
With progress of embedded system hardware, embedded system can provide more substrative supports for embedded operating systems.  ...  With progress of embedded system hardware, embedded system can provide more substrative supports for embedded operating systems.  ...  Most mobile devices have limited hardware support compared to PCs. And embedded operating systems for mobile devices have to base on this hardware.  ... 
doi:10.1007/11859802_46 fatcat:2vkhnz5qazc4fievcple7y62la

Compiler-Driven Leakage Energy Reduction in Banked Register Files [chapter]

David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa Lopez-Vallejo
2006 Lecture Notes in Computer Science  
It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent  ...  In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system.  ...  The register assignment is the phase of any compiler that determines which register(s) to use for each program value selected during register allocation, while the register allocation is the phase that  ... 
doi:10.1007/11847083_11 fatcat:cpfpkrmxaneinizhmwkciqjblq

BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management

Flavius Gruian, Mark Westmijze
2007 Ninth International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2007)  
This paper presents BLUEJAMM, a prototype architecture suitable for embedded systems based on a Java native processor.  ...  BLUEJEP, the processor, which is a microprogrammed pipelined stack machine, and its hardware memory management unit were developed in Bluespec Sys-temVerilog (BSV).  ...  Related Work Besides JOP [16] , which was the starting point for our processor, several designs for Java embedded processors were reported in the research community.  ... 
doi:10.1109/synasc.2007.12 dblp:conf/synasc/GruianW07 fatcat:cecp2y3cijf7xgiqf3rrvhfeky

A time-predictable stack cache

Sahar Abbaspour, Florian Brandner, Martin Schoeberl
2013 16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)  
In this paper we present the design and implementation of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache.  ...  ., heap allocated and stack allocated data) share the same cache. This sharing leads to less precise results of the cache analysis part of the WCET analysis.  ...  Acknowledgment This work was partially funded under the European Union's 7th Framework Programme under grant agreement no. 288008: Time-predictable Multi-Core Architecture for Embedded Systems (T-CREST  ... 
doi:10.1109/isorc.2013.6913225 dblp:conf/isorc/AbbaspourBS13 fatcat:2vzbswsosvgzfh2v2geekmjpby

Zikimi: A Case Study in Micro Kernel Design for Multimedia Applications

Sang-Yeob Lee, Youjip Won, Whoi-Yul Kim
2005 Multimedia tools and applications  
In this article, we like to present the details of design and implementation experience of low cost embedded system, Zikimi, for multimedia data processing.  ...  The result of performance experiment shows that LMS (linear memory system) of Zikimi micro kernel achieves significant performance improvement on memory allocation against legacy virtual memory management  ...  This port number depends on the video chip hardware. Port number 0x3c5 is used to specify the value for the register. We can retrieve the value of register in the same way.  ... 
doi:10.1007/s11042-005-3813-2 fatcat:4n3p3uzb5bhrplqpgtpijg5kuy

Hardware Concurrent Garbage Collection for Short-Lived Objects in Mobile Java Devices [chapter]

Chi Hang Yau, Yi Yu Tan, Anthony S. Fong, Wing Shing Yu
2005 Lecture Notes in Computer Science  
jHISC is an object-oriented processor for embedded system aiming at accelerating Java execution by hardware approach. Garbage collection is one of the critical tasks in a Java Virtual Machine.  ...  The hardware allocator provides a constant time object allocation.  ...  This paper introduces a hardware garbage collection method based on reference counting algorithm, for jHISC processor.  ... 
doi:10.1007/11596356_8 fatcat:hqcxl4x4aferlgloiv7afdprru
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