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Hardware–compiler co-design for adjustable data power savings

Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu
2009 Microprocessors and microsystems  
Building upon the compiler techniques presented in [1], we evaluate the severity of the current on-chip storage power problem and detail how SRAM structures can be built to enable data power savings for  ...  knowledge with an SRAM having variable latency and access properties, yielding adjustable power savings.  ...  Acknowledgments The authors would like to thank Shane Ryoo for his contributions to the memory profiler used in this work.  ... 
doi:10.1016/j.micpro.2009.02.003 fatcat:566u73invvbrflkbooart45gqe

TOWARDS GREEN COMPUTING, IMPORTANCE, IMPACT AND POSSIBLE SOLUTIONS-A REVIEW

Ambooj Yadav
2018 International Journal of Advanced Research in Computer Science  
accordingly [21] . 2) Software enegry saving a) Using compiling technology for energy saving: Compiler optimization is the most critical method of compiler design, mainly in high-performance compiler  ...  according to system operation state, which might offer full play to the energy-saving features of the low-power hardware.  ... 
doi:10.26483/ijarcs.v9i1.5299 fatcat:dsrkxeiumvfz7dyx62ov7bhy6a

A special-purpose compiler for look-up table and code generation for function evaluation

Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, Sai Prashanth Muralidhara, Hui Zhao, Mahmut Kandemir, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
The experimental results show that our solutions for function evaluation bring significant performance improvements to applications on multicores as well as significant resource savings to designs on FPGAs  ...  This paper presents a special-purpose compiler that automatically generates customized look-up tables and implementations for elementary functions under user given constraints.  ...  The report aims at helping the user adjust the high-level resource assignments among different modules in a hardware design. VII.  ... 
doi:10.1109/date.2010.5456978 dblp:conf/date/ZhangDYMZKCPS10 fatcat:ebwxtrlhrbbt5e4wlhsj47livi

Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view [chapter]

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996 Lecture Notes in Computer Science  
So far all the CCM scenes mainly cover a kind of hardware/software co-design approach. But an open question is: what is the difference between CCM design and H/S co-design?  ...  Both scenes have strong relations to Hardware/Software Co-Design. CCMs are mainly based on field-programmable add-on hardware to accelerate microprocessors or computers.  ...  ASIP design means designing appication-specific hardware, rather then H/S co-design Co-Design focuses on the hardware/software partitioning problem.  ... 
doi:10.1007/3-540-61730-2_7 fatcat:td6e4mto2jaaxixzgf6kxifefa

Guest Editors' Introduction to the Special Issue on Machine Learning Architectures and Accelerators

Xuehai Qian, Yanzhi Wang, Avinash Karanth
2020 IEEE transactions on computers  
(weight pruning, quantization, matrix transformation, etc.), compiler-assisted optimizations, parallel computing techniques such as data parallelism and model parallelism, distributed training algorithms  ...  The training phase of the application is highly computation and data-intensive, and thus software/algorithm optimization as well as hardware acceleration re critically required.  ...  We also would like to thank the anonymous reviewers for their invaluable help in evaluating and judging the submissions.  ... 
doi:10.1109/tc.2020.2997574 fatcat:vfng262tlvagrmfudtv44x75ly

A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach

Agus Bejo, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda
2014 Journal of Information Processing  
A complete set of software development tools consisting of a compiler, assembler, disassembler, linker, debugger, simulator and also hardware implementation for the modified ASIP architecture can be generated  ...  With our proposed tool, a new co-processor/instruction extension can be designed and added to the base architecture more easily.  ...  This makes behavioral-based ADL more suitable for compiler generation but not for hardware synthesis generation.  ... 
doi:10.2197/ipsjjip.22.131 fatcat:gvj3mpyvfbae7httsxglmetkue

Architecture support for disciplined approximate programming

Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger
2012 Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '12  
The basis of our design is dual-voltage operation, with a high voltage for precise operations and a low voltage for approximate operations.  ...  We evaluate the power savings potential of in-order and out-of-order Truffle configurations and explore the resulting quality of service degradation.  ...  Acknowledgments We would like to thank the anonymous reviewers for their valuable comments.  ... 
doi:10.1145/2150976.2151008 dblp:conf/asplos/EsmaeilzadehSCB12 fatcat:zo4r7jgjhbbmdb7cng7y3oxfzm

Architecture support for disciplined approximate programming

Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger
2012 SIGARCH Computer Architecture News  
The basis of our design is dual-voltage operation, with a high voltage for precise operations and a low voltage for approximate operations.  ...  We evaluate the power savings potential of in-order and out-of-order Truffle configurations and explore the resulting quality of service degradation.  ...  Acknowledgments We would like to thank the anonymous reviewers for their valuable comments.  ... 
doi:10.1145/2189750.2151008 fatcat:hpik6qqk2nckvc5pjm3ndike6y

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Ahmed A. Eltawil, Michael Engel, Bibiche Geuskens, Amin Khajeh Djahromi, Fadi J. Kurdahi, Peter Marwedel, Smail Niar, Mazen A.R. Saghir
2013 Microprocessors and microsystems  
This paper surveys various cross layer techniques and approaches for power, performance, and reliability tradeoffs are technology, circuit, architecture and application layers.  ...  Today, designers must consider building systems that achieve the requisite functionality and performance using components that may be unreliable.  ...  ERSA [63] is a more drastic technique for saving power on a multicore architecture.  ... 
doi:10.1016/j.micpro.2013.07.008 fatcat:bl2v6dfvxnfxnble4pkcg2pcw4

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures [chapter]

G. Durelli, M. Coppola, K. Djafarian, G. Kornaros, A. Miele, M. Paolino, Oliver Pell, Christian Plessl, M. D. Santambrogio, C. Bolchini
2014 Lecture Notes in Computer Science  
Self-adaptiveness and hardware-assisted virtualization are the two key-enabling technologies for this kind of architectures, to allow the efficient exploitation of the available resources based on the  ...  The SAVE project will develop HW/SW/OS components that allow for deciding at runtime the mapping of the computation kernels on the appropriate type of resource, based on the current system context and  ...  co-processors via PCI express/Infiniband for the HPC domain.  ... 
doi:10.1007/978-3-319-05960-0_38 fatcat:txyxyy3oxfgxxlejazrypktzti

Hardware and software techniques for controlling DRAM power modes

V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M.J. Irwin
2001 IEEE transactions on computers  
Index TermsÐMemory architecture, low power, low power compilation, software-directed energy management. ae  ...  This paper conducts an in-depth investigation of software and hardware techniques to take advantage of the DRAM mode control capabilities at a module granularity for energy savings.  ...  This paper has been enhanced to provide more details on our approach and also includes additional compiler optimizations to exploit low power modes.  ... 
doi:10.1109/12.966492 fatcat:q2tjhu3o2vgdlf6yxe562aajn4

Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems

Giovanni Agosta, Gianluca Palermo, Cristina Silvano
2004 Proceedings of the 2004 ACM symposium on Applied computing - SAC '04  
This paper proposes a methodology for the co-exploration of the design space composed of architectural parameters and source program transformations.  ...  The exploration of the architectural design space in terms of energy and performance is of mainly importance for a broad range of embedded platforms based on the System-On-Chip approach.  ...  CONCLUSIONS AND FUTURE WORKS Our work presents a co-exploration of the architectural and transformation spaces supporting the design of mixed hardware and software systems for embedded low-power applications  ... 
doi:10.1145/967900.968080 dblp:conf/sac/AgostaPS04 fatcat:s4piw64vhzbk5haccc4r3prh34

Coordinating System Software for Power Savings

Lingxiang Xiang, Jiangwei Huang, Tianzhou Chen
2008 2008 Second International Conference on Future Generation Communication and Networking  
software, especially the operation system and compiler, are collaborating toward file-grain power optimizations.  ...  This paper presents coordination mechanisms that integrate operating systems with compilers under power reduction techniques such as DPM and DVS.  ...  The power-aware scheduler achieves energy savings about 10% with little performance loss for some situations, while the compiler assisted DPM policy with I/O predication can save more than 12% power compared  ... 
doi:10.1109/fgcn.2008.127 dblp:conf/fgcn/XiangHC08 fatcat:2kecyuhchvgfhhl7zpezjpqzce

Automatic Application Specific Floating-point Unit Generation

Yee Jern Chong, Sri Parameswaran
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Area savings over a fully-featured FPU without resource sharing of 26%-80% without resource sharing and 33%-87% with resource sharing, were obtained.  ...  On the other hand, using a predefined FPU includes a large monolithic hardware block with considerable number of unused instructions.  ...  This reduces redundant resources and results in area and power savings. To reduce cost, area and power, it is desirable for the FPU to have as few hardware blocks and interconnections as possible.  ... 
doi:10.1109/date.2007.364635 dblp:conf/date/ChongP07 fatcat:eqydhaq4vrgubfdvtz6pq6utgq

Compiler Directed Speculative Intermittent Computation [article]

Jongouk Choi, Qingrui Liu, Changhee Jung
2020 arXiv   pre-print
This paper presents CoSpec, a new architecture/compiler co-design scheme that works for commodity in-order processors used in energy-harvesting systems.  ...  CoSpec compiler first partitions a given program into a series of recoverable code regions with the SB size in mind, so that no region overflows the SB.  ...  We appreciate anonymous reviewers for their constructive comments. This work was supported by NSF grants 1750503 (CAREER Award) and 1814430.  ... 
arXiv:2006.11479v1 fatcat:iksj4lk5qbdbtcplf7f33wwfnm
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