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Hardware-Assisted Code Obfuscation for FPGA Soft Microprocessors
2015
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
unpublished
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The availability of specialization in FPGAs provides a unique opportunity for code obfuscation on a per-application basis with minimal hardware overhead. ...
In this paper we describe a new technique to obfuscate soft microprocessor code which is located outside the FPGA chip in an unprotected area. ...
CONCLUSIONS AND FUTURE WORK In this paper we have described an FPGA-specific technique to obscure code executed by FPGA soft microprocessors. ...
doi:10.7873/date.2015.0498
fatcat:yu6ukozrkrbmdo2u5jkr2nowee
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors
2018
IEEE transactions on computers
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We employ a fine-grained, hardware-enforced access control mechanism for information exchange with the processor and hardware-assisted booby traps to actively counteract manipulation attacks. ...
Both measures are based on a compiler which generates obfuscated programs, and an embedded processor implemented in an FPGA with a randomized ISA encoding to execute the hybrid obfuscated program. ...
Furthermore, we would like to thank the anonymous reviewers for their valuable comments. ...
doi:10.1109/tc.2017.2649520
fatcat:p332lanfhfcijnqpusljfxqyr4
FPGA-Based Remote-Code Integrity Verification of Programs in Distributed Embedded Systems
2012
IEEE Transactions on Systems Man and Cybernetics Part C (Applications and Reviews)
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This paper proposes the use of reconfigurable computing to build a consistent architecture for generating attestations (proofs) of code integrity for an executing program, and for delivering them to the ...
Among the different challenges in software security, the problem of remote code integrity verification is still waiting for efficient solutions. ...
The FPGA hosts a soft hardware component referred to as hardware monitor (HM ). ...
doi:10.1109/tsmcc.2011.2106493
fatcat:7sbaap5yarhplci7kentk42qhq
Securing Soft IP Cores in FPGA based Reconfigurable Mobile Heterogeneous Systems
[article]
2019
arXiv
pre-print
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In this paper we propose two different protocols suitable for the secure deployment of soft IP cores in FPGA-based mobile heterogeneous systems where multiple independent actors are involved: a simple ...
In particular, protecting the Intellectual Property of the exchanged soft IP cores is a serious concern. ...
The authors of [26] leverage FPGA dark silicon to obfuscate the functionality of the design. ...
arXiv:1912.00696v1
fatcat:hzog3clk7ngwvi73f4jj4djpry
2018 Index IEEE Transactions on Computers Vol. 67
2019
IEEE transactions on computers
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., þ, TC Aug. 2018 1136-1152 Leveraging Hardware-Assisted Virtualization for Deterministic Replay on Commodity Multi-Core Processors. ...
., þ, TC March 2018 375-387
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded
Microprocessors. ...
doi:10.1109/tc.2018.2882120
fatcat:j2j7yw42hnghjoik2ghvqab6ti
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
2010
ACM Transactions on Reconfigurable Technology and Systems
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, a commercial HLL for FPGAs. ...
for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). ...
For Impulse C, reverse mapping is currently tool assisted. ...
doi:10.1145/1661438.1661443
fatcat:l6tx47n65fdihbonb2kjqdwtk4
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security
2021
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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We will discuss the possible future research directions, and thereby, sharing a roadmap for the hardware security community in general. ...
On the other hand, ML-based approaches have also been adopted by adversaries to assist side-channel attacks, reverse engineer integrated circuits and break hardware security primitives like Physically ...
[199] proposed an obfuscation framework that utilizes hardware-assisted IP protection scheme for DL models. A key-dependent backpropagation algorithm is employed to train the neural network model. ...
doi:10.1109/jetcas.2021.3084400
fatcat:c4wdkghpo5fwbhvkekaysnahzm
A survey of the RISC-V architecture software support
2022
IEEE Access
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Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular tool-chains and operating systems already have support for RISC-V. ...
However, although many works have been exploring the RISC-V software ecosystem, no work that raised the current state of software support for RISC-V is available. ...
Similarly, [97] evaluate the reliability of software applications running on soft microprocessors against SEUs that affect configuration and microprocessor memories. ...
doi:10.1109/access.2022.3174125
fatcat:smbyxselm5gjxlk4pqilzrxjli
Fault Tolerance & Testable Software Security: A Method of Quantifiable Non-Malleability with Respect to Time
2007
2007 Canadian Conference on Electrical and Computer Engineering
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non-malleability) of software with respect to time a property to the best of our knowledge not demonstrated previously; this in turn, implies practical limits to software security using current existing processing hardware ...
Given the recoverability limitation, we demonstrate a quantifiable definition for secure software with respect to integrity/tamper resistance. ...
FPGAs are often referred to as soft hardware as they implement the gates and logic of hard silicon; the difference is that FPGA's can be reprogrammed whereas silicon processors cannot. ...
doi:10.1109/ccece.2007.386
fatcat:pyhkspnivnevxcpjwfftbn4cfm
A CRISPR-Cas-Inspired Mechanism for Detecting Hardware Trojans in FPGA Devices
[article]
2020
arXiv
pre-print
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We propose a CRISPR-Cas-inspired (clustered regularly interspaced palindromic repeats) method for detecting hardware Trojans in FPGAs. ...
Existing methods for hardware Trojan detection in FPGA (field programmable gate array) devices include test-time methods, pre-implementation methods, and run-time methods. ...
ACKNOWLEDGMENT The authors thank the University of Cincinnati and the Air Force Research Laboratory for providing the support and resources necessary for success. ...
arXiv:2005.07332v1
fatcat:iusvndz7fjc2lbwfdrrf7hnusq
HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs
2012
International Journal of Reconfigurable Computing
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Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. ...
We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend and insert ...
from the FASTA35 code package [30] . ...
doi:10.1155/2012/162404
fatcat:zazovrcwnnfspn53csbp6vr53y
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
2011
2011 21st International Conference on Field Programmable Logic and Applications
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Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. ...
interface directly to a running design on an FPGA. ...
HLV can assist even during later stages of development by for hardware re-implementation, but rather the time required to recompile and reintegrate the software into the hardware bitstream. ...
doi:10.1109/fpl.2011.102
dblp:conf/fpl/IskanderPC11
fatcat:3m3crbq42remvh6d7oz6ftpexu
Cybersecurity: Past, Present and Future
[article]
2022
arXiv
pre-print
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The main specializations of cybersecurity covered in this book are software security, hardware security, the evolution of malware, biometrics, cyber intelligence, and cyber forensics. ...
One of the methods used to implement this mechanism is in the microprocessor hardware. ...
Code Obfuscation To protect software we want to make exploitation of vulnerabilities harder. One of the basic techniques used for this purpose is code obfuscation. ...
arXiv:2207.01227v1
fatcat:vfx54hq3ejc7dlfestj6dkstpa
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J ...
., +, TVLSI Oct. 2018 2118-2131 ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
Energy-Efficient Neuromorphic Classifiers
2016
Neural Computation
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Until now, however, the neuromorphic approach has been restricted to relatively simple circuits and specialized functions, thereby obfuscating a direct comparison of their energy consumption to that used ...
Moreover, the spike-based dynamics display a trade-off between integration time and accuracy, which naturally translates into algorithms that can be flexibly deployed for either fast and approximate classifications ...
Modha for their assistance with the IBM chip simulator. In particular, we thank John Arthur and Paul Merolla for their help with the estimate of the chip energy consumption. ...
doi:10.1162/neco_a_00882
pmid:27557100
fatcat:2vgueef2y5c5lmpcfkbwi52wdi
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