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Use of Formal Verification at Centaur Technology [chapter]

Warren A. Hunt, Sol Swords, Jared Davis, Anna Slobodova
2010 Design and Verification of Microprocessor Systems for High-Assurance Applications  
We verify Verilog designs by first translating them into a formally defined hardware description language, and then using a variety of automated verification algorithms controlled by theorem-proving scripts  ...  Overview of Verification Methodology In our verification process, we first translate the Verilog RTL source code of Centaur's design into EMOD, a formally defined HDL.  ...  We would also like to thank Bob Boyer for development of much of the technology behind EMOD and the ACL2 BDD package, Terry Parks for developing a very detailed floating-point addition specification, and  ... 
doi:10.1007/978-1-4419-1539-9_3 fatcat:qczrzp6ah5a5lmq75hllk6oymq

Multipliers and dividers: Insights on arithmetic circuit verification (extended abstract) [chapter]

Randal E. Bryant
1995 Lecture Notes in Computer Science  
These two classes of functions can be represented and manipulated as ordered Binary Decision Diagrams (BDDs), and Binary Moment Diagrams (BMDs), respectively.  ...  Much of the research in formal hardware verification has focussed on systems having complex control, but relatively simple data operations.  ...  Much of the research in formal hardware verification has focussed on systems having complex control, but relatively simple data operations.  ... 
doi:10.1007/3-540-60045-0_35 fatcat:r7txrp5sonaczc54oudz222cee

On The Integration of Decision Diagrams in High Order Logic Based Theorem Provers:a Survey

Sa'ed Abed, Otmane Ait Mohamed, Ghiath Al Sammane
2007 Journal of Computer Science  
This survey discuss approaches that integrate Decision Diagrams inside High Order Logic based Theorem provers.  ...  [5] used higher order hardware formulae to express the safety and liveness properties hierarchically.  ...  Theorem Proving is an approach where the specification and the implementation are usually expressed in first-order or higher-order logic.  ... 
doi:10.3844/jcssp.2007.810.817 fatcat:gu5y5qe4azbpblxoebifj6ys5a

Formal Methods for Functional Verification [chapter]

Randal E. Bryant, James H. Kukula
2003 The Best of ICCAD  
Formal hardware design verification appears to have developed in the 1970's from earlier work in hardware testing and in software verification [23] .  ...  This allowed many BDD-based applications to be "retrofitted" to use dynamic variable ordering with only minor changes.  ... 
doi:10.1007/978-1-4615-0292-0_1 fatcat:t776pq6t7reyffs327dkmonjse

The implicit set paradigm: A new approach to finite state system verification

O. Coudert, J. C. Madre
1995 Formal methods in system design  
The computational costs of the verification procedures using this paradigm depend on the costs of the operations performed on this implicit representation instead of the number of states and transitions  ...  This paradigm allows these new verification procedures to overcome the limitations of previously available techniques.  ...  The explanation for such a behaviour is that the variable ordering used to build these BDDs is not a good variable ordering.  ... 
doi:10.1007/bf01383965 fatcat:hoaxmjw32rb2tfnowrd6gvn7di

Behavior Driven Development for Tests and Verification [chapter]

Melanie Diepenbeck, Rolf Drechsler
2015 Formal Modeling and Verification of Cyber-Physical Systems  
The design of hardware systems is a challenging and errorprone task, where a signifcant portion of the effort is spent for testing and verification.  ...  The flow also includes an automatic generalisation of test cases to properties that are used for formal verification.  ...  First, the used property specification language and the basics of BDD are introduced in Sect. 2. The proposed BDD flow for hardware design and verification are presented in Sect. 3.  ... 
doi:10.1007/978-3-658-09994-7_11 dblp:conf/syde/DiepenbeckD15 fatcat:nimra7s25rafhdyexbyarsvnj4

Behaviour Driven Development for Hardware Design

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Grosse, Rolf Drechsler
2018 IPSJ Transactions on System LSI Design Methodology  
In this article, we show how BDD can be extended to make it viable for hardware design.  ...  Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers.  ...  Testing Hardware Designs with BDD In order to inspect a hardware design, a testbench is written that simulates the design under test.  ... 
doi:10.2197/ipsjtsldm.11.29 fatcat:5yku64v3ljactlpjnup7jt26oa

Practical formal verification in microprocessor design

R.B. Jones, J.W. O'Leary, C.-J.H. Seger, M.D. Aagaard, T.F. Melham
2001 IEEE Design & Test of Computers  
Each case required a different BDD variable ordering. We easily generated the case splits and variable orderings using an FL script.  ...  It is a useful first step, but industrial hardware verification is very challenging, and much work remains in defining the methodology and the underlying technology.  ...  How to Contact Us Reprints of Articles For price information or to order reprints, send e-mail to or fax to IEEE Design & Test at (714) 821-4010.  ... 
doi:10.1109/54.936245 fatcat:wasuwsfdffgnboeyfpyu47tjvy

Hybrid verification using saturated simulation

Adnan Aziz, Jim Kukula, Tom Shiple
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
We develop a verification paradigm called saturated simulation, that is applicable to designs which can be decomposed into a set of interacting controllers.  ...  Background In order to analytically reason about hardware, we first need to develop mathematical models for digital systems.  ...  Netlists and FSMs Hardware can be modeled at the structural level using netlists, or at the behavioral level using finite state machines (FSMs).  ... 
doi:10.1145/277044.277204 dblp:conf/dac/AzizKS98 fatcat:lmmfklqea5colb5ir6kfxuyzie

SAT-Based Verification Methods and Applications in Hardware Verification [chapter]

Aarti Gupta, Malay K. Ganai, Chao Wang
2006 Lecture Notes in Computer Science  
This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs.  ...  Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods.  ...  The first two case studies do not contain large embedded memories, and use the verification flow shown in Figure 16 (a).  ... 
doi:10.1007/11757283_5 fatcat:5kb2pmlvjvat5ljeei2fflzufa

Automatic datapath extraction for efficient usage of HDD [chapter]

Gila Kamhi, Osnat Weissberg, Limor Fix, Ziv Binyamini, Ze'ev Shtadler
1997 Lecture Notes in Computer Science  
However, extensive user interaction with the formal verification tool was required in order to use the HDD technology efficiently.  ...  Moreover, the partitioning algorithm decides which vector operations will be represented more efficiently as word-level (i.e. using HDD) versus bit-level (i.e using BDD).  ...  In Section 5, we will present the algorithm currently used by Prover in order to decide which portion of the logic will be represented as BDD and which portion of the logic will be represented as BMD.  ... 
doi:10.1007/3-540-63166-6_12 fatcat:kmcbfvggdrdsndzlcy2htkyw7e


Robert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün
2012 Formal methods in system design  
In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and then describe a co-verification methodology developed using  ...  We focus on techniques that have proved successful in each of the two domains: BDD-based symbolic model checking for hardware verification and partial order reduction for the verification of concurrent  ...  Acknowledgments We thank James Browne, Fei Xie and Natasha Sharygina for their valuable contributions that assisted our method to mature, and the reviewers for their useful comments. Notes  ... 
doi:10.1023/a:1020383505582 fatcat:guk6vrqfunbrfhuiqrl7bsklla

Exploiting structural similarities in a BDD-based verification method [chapter]

C. A. J. Eijk, G. L. J. M. Janssen
1995 Lecture Notes in Computer Science  
A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size.  ...  We explain how these similarities can be detected and put to effective use in the verification process.  ...  Acknowledgements We kindly acknowledge IBM Corporation, Yorktown, for making their BSN design system available to us.  ... 
doi:10.1007/3-540-59047-1_45 fatcat:k2ujcjlspzconav5hubyge4eda

Effective theorem proving for hardware verification [chapter]

D. Cyrluk, S. Rajan, N. Shankar, M. K. Srivas
1995 Lecture Notes in Computer Science  
We describe an approach for enhancing the effectiveness of theorem provers for hardware verification through the use of efficient automatic procedures for rewriting, arithmetic and equality reasoning,  ...  The attractiveness of using theorem provers for system design verification lies in their generality.  ...  This system does incorporate first-order BDD-based techniques that can handle some data types and parameterized hardware.  ... 
doi:10.1007/3-540-59047-1_50 fatcat:zwwryahpejavfleqthleuefjjq

Constraint synthesis for environment modeling in functional verification

Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verification.  ...  Constraint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don't care information unique to hardware constraints and heuristic variable removal  ...  INTRODUCTION Constraint-based verification is the idea of defining an environment for the Design Under Verification (DUV) by using constraints.  ... 
doi:10.1145/775905.775909 fatcat:wwn2hm2utnbd7gijuzoj74ngq4
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